comp.arch.fpga
- synthesis tools,
axr0284
- Re: synthesis tools, Jon Beniston
- Re: synthesis tools, Mike Treseler
- Please help me fast !!!!!,
rogodani
- Re: Please help me fast !!!!!, Benjamin Todd
- Re: Please help me fast !!!!!, John_H
- Re: Please help me fast !!!!!, Paul
- Re: Please help me fast !!!!!, tersono
- Re: Please help me fast !!!!!, Jeff Cunningham
- ise9.1i regid not working on x64, Morten Leikvoll
- DDR2 with Spartan-3A anybody having success??, Antti
- weird PACE Error, not one google result, mludwig
- Xilinx software quality - how low can it go ?!, Antti
- SAE j1850 pwm protocol controller ip core, ashasravanthi
- Serial FPDP, eapen . abraham
- Re: debounce state diagram FSM, Jim Granville
- DS18B20 connection on FPGA?,
Mad I.D.
- Re: DS18B20 connection on FPGA?, Jeff Cunningham
- Macro modified after Map ?, Pasacco
- Interconnect architectures : Aurora and SPI-S, fluxgate
- driving Spartan-3 input from 74LS TTL,
Eric Smith
- Re: driving Spartan-3 input from 74LS TTL,
Jim Granville
- Re: driving Spartan-3 input from 74LS TTL,
Peter Alfke
- Re: driving Spartan-3 input from 74LS TTL, Eric Smith
- Re: driving Spartan-3 input from 74LS TTL, Peter Alfke
- Re: driving Spartan-3 input from 74LS TTL, Nico Coesel
- Re: driving Spartan-3 input from 74LS TTL, Jim Granville
- Re: driving Spartan-3 input from 74LS TTL,
Peter Alfke
- Re: driving Spartan-3 input from 74LS TTL,
Jim Granville
- How many Xilinx devkits does one need?, Antti
- TigerSHARC TS201 to PLX 9656,
eapen . abraham
- Re: TigerSHARC TS201 to PLX 9656,
Gabor
- Re: TigerSHARC TS201 to PLX 9656, eapen . abraham
- Re: TigerSHARC TS201 to PLX 9656,
colin
- Re: TigerSHARC TS201 to PLX 9656, Ron Huizen
- Re: TigerSHARC TS201 to PLX 9656,
Gabor
- Is there a reset signal available in verilog in Xilinx FPGAs?, janbeck
- Placement error for adjacent pins,
M. Hamed
- Re: Placement error for adjacent pins,
Gabor
- Re: Placement error for adjacent pins, M. Hamed
- Re: Placement error for adjacent pins, Nico Coesel
- Re: Placement error for adjacent pins,
Gabor
- Killed a Stratix-II Nios II Altera devkit, How to repair?, bfroemel
- constraints for design-generated clock, mludwig
- Problem cascading 2 DCMs,
MNiegl
- Re: Problem cascading 2 DCMs,
Nico Coesel
- Re: Problem cascading 2 DCMs, MNiegl
- Re: Problem cascading 2 DCMs, Peter Alfke
- Re: Problem cascading 2 DCMs,
Austin Lesea
- Re: Problem cascading 2 DCMs,
MNiegl
- Re: Problem cascading 2 DCMs, Alvin Andries
- Re: Problem cascading 2 DCMs, MNiegl
- Re: Problem cascading 2 DCMs, Erik Widding
- Re: Problem cascading 2 DCMs,
MNiegl
- Re: Problem cascading 2 DCMs,
Symon
- Re: Problem cascading 2 DCMs,
MNiegl
- Re: Problem cascading 2 DCMs, Gabor
- Re: Problem cascading 2 DCMs, MNiegl
- Re: Problem cascading 2 DCMs,
MNiegl
- Re: Problem cascading 2 DCMs,
Rob Dimond
- Re: Problem cascading 2 DCMs, MNiegl
- Re: Problem cascading 2 DCMs,
Nico Coesel
- chip to chip high speed interconnet bus, bjzhangwn@xxxxxxxxx
- a question about DDFS,
fp
- Re: a question about DDFS, Peter Alfke
- Prope timing constraint for this pin?, jetmarc
- one extra slipway board from fccm,
Adam Megacz
- Re: one extra slipway board from fccm,
fpga_toys
- Re: one extra slipway board from fccm, comp.arch.fpga
- Re: one extra slipway board from fccm,
fpga_toys
- N00b question about DCM,
Bob
- Re: N00b question about DCM, Sylvain Munaut
- Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?,
mohan
- Re: Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?, Colin Paul Gloster
- Re: Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?, cs_posting
- Re: Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?, Daniel O'Connor
- Quartus Fitter Seed Setting,
jjlindula@xxxxxxxxxxx
- Re: Quartus Fitter Seed Setting, Ben Twijnstra
- memory interface for DDR/DDR2 with xilinx spartan 3E/3A starter kits, rponsard
- Question about the simulation library in Xilinx EDK, Rebecca
- Question about the simulation library in EDK,
Rebecca
- <Possible follow-ups>
- Question about the simulation library in EDK, Rebecca
- Question about the simulation library in EDK, Rebecca
- Sscanf replacement for xilinx EDK,
jmariano
- Re: Sscanf replacement for xilinx EDK, Nico Coesel
- Re: Sscanf replacement for xilinx EDK, Gabor
- Re: Sscanf replacement for xilinx EDK, zcsizmadia@xxxxxxxxx
- Re: Sscanf replacement for xilinx EDK, jmariano
- differential pins assignment in Synplify fro altera device, zibixx76
- pcis3base, cesys, S.j
- Need help: Altera ALTPLL_RECONFIG state machine construction, Bob
- WebPACK 9.1i still makes errors with synthesis of BRAMS, user
- Is microblaze able to change heap_size?, Pablo
- How to configure SPI FLASH using Spartan-3E?,
Sven
- Re: How to configure SPI FLASH using Spartan-3E?, Eric Crabill
- Altera Quartus II v7.0 under openSUSE 10.2,
Markus Kuhn
- Re: Altera Quartus II v7.0 under openSUSE 10.2, Ben Twijnstra
- How to drop a Ethernet Packet in Xilinx EMAC, Venu
- Timing constraints with asynchronous clocks, M. Hamed
- interrupt handler on the Xilkernel PPC405,
zl
- Re: interrupt handler on the Xilkernel PPC405, Roman
- <Possible follow-ups>
- interrupt handler on the Xilkernel PPC405, zl
- Memory Resource in SDRAM, pantgom
- test, js
- Increase Memory Resource in SDRAM.,
Pablo
- Re: Increase Memory Resource in SDRAM.,
Ben Jones
- Re: Increase Memory Resource in SDRAM.,
Pablo
- Re: Increase Memory Resource in SDRAM., Andreas Hofmann
- Re: Increase Memory Resource in SDRAM., Pablo
- Re: Increase Memory Resource in SDRAM.,
Pablo
- Re: Increase Memory Resource in SDRAM.,
Ben Jones
- OPB master and slave interface for DDR SDRAM controller, 마쉬
- Using OPB PCI In EDK 8.1, maverick
- physical chip size,
Pasacco
- Re: physical chip size,
Peter Alfke
- Re: physical chip size,
Pasacco
- Re: physical chip size, Jim Granville
- Re: physical chip size,
Pasacco
- Re: physical chip size, comp.arch.fpga
- Re: physical chip size,
Peter Alfke
- Re: physical chip size,
Pasacco
- Re: physical chip size, Peter Alfke
- Re: physical chip size, comp.arch.fpga
- Re: physical chip size, Daniel S.
- Re: physical chip size,
Pasacco
- <Possible follow-ups>
- Physical chip size, Pasacco
- Re: physical chip size,
Peter Alfke
- Virtex-5 FX when ? (II),
Udo
- Re: Virtex-5 FX when ? (II),
Sean Durkin
- Re: Virtex-5 FX when ? (II), Antti
- Re: Virtex-5 FX when ? (II),
Sean Durkin
- Image compression on FPGA,
eric
- Re: Image compression on FPGA, Thomas Entner
- Re: Image compression on FPGA, David M. Palmer
- Using OPB PCI Bridge in EDK 8.2i, sheikh . m . farhan
- Using PCI in EDK 8.21, sheikh . m . farhan
- Incorrect response from MAC FIR Low Pass Filter, Bryan
- compact flash slave ip core, bjzhangwn@xxxxxxxxx
- XPS and inout ports: is it possible?, IB
- Problem with PowerPC PIT interrupt,
Matthew Hicks
- Re: Problem with PowerPC PIT interrupt,
Martin Thompson
- Re: Problem with PowerPC PIT interrupt, Matthew Hicks
- Re: Problem with PowerPC PIT interrupt, Alan Nishioka
- Re: Problem with PowerPC PIT interrupt,
Matthew Hicks
- Re: Problem with PowerPC PIT interrupt,
Matthew Hicks
- Re: Problem with PowerPC PIT interrupt, Alan Nishioka
- Re: Problem with PowerPC PIT interrupt, leevv
- Re: Problem with PowerPC PIT interrupt,
Matthew Hicks
- Re: Problem with PowerPC PIT interrupt,
Martin Thompson
- The simulation library compilation wizard of EDK can't find modelsim,
Rebecca
- <Possible follow-ups>
- The simulation library compilation wizard of EDK can't find modelsim, Rebecca
- EDK Simulation library compilation wizard can't find modelsim, Rebecca
- Increase memory resource at Xil_malloc., Pablo
- Is anyone has experience to share OPB for 2 PowerPC in MPMC2 core, js
- FPGA and DAC for wave generation,
Sheetal
- Re: FPGA and DAC for wave generation, cs_posting
- Re: FPGA and DAC for wave generation, Gabor
- Re: FPGA and DAC for wave generation, Peter Alfke
- Re: FPGA and DAC for wave generation, -jg
- How to add customer peripheral with IP core to EDK?,
FPGA
- Re: How to add customer peripheral with IP core to EDK?, swamy_digital
- I make a usb blaster for altera by myself!,
lzh08
- Re: I make a usb blaster for altera by myself!, Symon
- Re: I make a usb blaster for altera by myself!, Mark McDougall
- Take verilog code from Xilinx Core generator, Gordon Freeman
- XTREME DSP Development Kit2 JTAG Problem,
Bryan
- Re: XTREME DSP Development Kit2 JTAG Problem, mtsukanov
- Slave PLB core interrupt,
Manny
- Re: Slave PLB core interrupt,
jetmarc
- Re: Slave PLB core interrupt, Manny
- Re: Slave PLB core interrupt,
jetmarc
- I/O-Standards: HSTL vs. SSTL and others...,
Udo
- Re: I/O-Standards: HSTL vs. SSTL and others..., Austin Lesea
- free architecture,
Jhoberg
- Re: free architecture, Jhoberg
- <Possible follow-ups>
- free architecture, Jhoberg
- V5 GTP question,
Test01
- Re: V5 GTP question, Austin Lesea
- Re: V5 GTP question,
Test01
- Re: V5 GTP question,
Austin Lesea
- Re: V5 GTP question, Test01
- Re: V5 GTP question, Ed McGettigan
- Re: V5 GTP question, Test01
- Re: V5 GTP question,
Austin Lesea
- Problem with real data type,
Hrishi
- Re: Problem with real data type,
MM
- Re: Problem with real data type,
comp.arch.fpga
- VHDL support from vendors (from "Re: Problem with real data type"), Colin Paul Gloster
- Re: Problem with real data type,
comp.arch.fpga
- <Possible follow-ups>
- Problem with real data type,
Hrishi
- Re: Problem with real data type, comp.arch.fpga
- Re: Problem with real data type, Colin Paul Gloster
- Re: Problem with real data type,
MM
- Non-intrusive readback on FPGA configuration data, Pepi
- DONE problems,
ddallen
- Re: DONE problems,
Gabor
- Re: DONE problems, Dave
- Re: DONE problems,
kevin
- Re: DONE problems, Dave
- Re: DONE problems,
Gabor
- VHDL editing with UltraEdit,
mans
- Re: VHDL editing with UltraEdit,
wallge
- Re: VHDL editing with UltraEdit,
Nicolas Matringe
- Re: VHDL editing with UltraEdit, Andreas Ehliar
- Re: VHDL editing with UltraEdit, Martin Thompson
- Re: VHDL editing with UltraEdit, mans
- Re: VHDL editing with UltraEdit, Martin Thompson
- Re: VHDL editing with UltraEdit, Andreas Ehliar
- Re: VHDL editing with UltraEdit,
Colin Paul Gloster
- Re: VHDL editing with UltraEdit, Andy
- Re: VHDL editing with UltraEdit, Joseph Samson
- Re: VHDL editing with UltraEdit, Colin Paul Gloster
- Re: VHDL editing with UltraEdit, Martin Thompson
- Re: VHDL editing with UltraEdit, Martin Thompson
- Re: VHDL editing with UltraEdit,
Nicolas Matringe
- Re: VHDL editing with UltraEdit,
wallge
- Lattice pricing,
Richard Klingler
- Re: Lattice pricing, Jim Granville
- Symbol names in the Design Hierarchy Window of the Xilinx Floorplanner, MM
- Raggedstone1 LVDS Oscillator, John Adair
- simulating with OSe 9.1.3, mans
- Memory generator IP core ISE Webpack, Steve Battazzo
- Ouputs during startup and Programming,
Ed
- Re: Ouputs during startup and Programming,
Rob
- Re: Ouputs during startup and Programming,
Peter Alfke
- Re: Ouputs during startup and Programming, david.oriot
- Re: Ouputs during startup and Programming, Newman
- Re: Ouputs during startup and Programming, Peter Alfke
- Re: Ouputs during startup and Programming, Austin Lesea
- Re: Ouputs during startup and Programming, Rob
- Re: Ouputs during startup and Programming,
Peter Alfke
- Re: Ouputs during startup and Programming, Jim Granville
- Re: Ouputs during startup and Programming,
Rob
- Question about intalling EDK9.1i, Rebecca
- Looking for a spartan 3 board,
Thomas Heller
- Re: Looking for a spartan 3 board,
Gabor
- Re: Looking for a spartan 3 board,
Thomas Heller
- Re: Looking for a spartan 3 board, John Adair
- Re: Looking for a spartan 3 board,
Thomas Heller
- Re: Looking for a spartan 3 board,
Gabor
- FPGA Newbie,
Matt Sorrensen
- Re: FPGA Newbie, John Adair
- Re: FPGA Newbie,
Symon
- Re: FPGA Newbie,
Gabor
- Re: FPGA Newbie, Matt Sorrensen
- Re: FPGA Newbie, Jonathan Bromley
- Re: FPGA Newbie,
Gabor
- Re: FPGA Newbie,
Icky Thwacket
- Re: FPGA Newbie,
Jim Granville
- Re: FPGA Newbie, Matt Sorrensen
- Re: FPGA Newbie, Jim Granville
- Re: FPGA Newbie, David Kelly
- Re: FPGA Newbie, cs_posting
- Re: FPGA Newbie, Jim Granville
- Re: FPGA Newbie, Mike Harrison
- Re: FPGA Newbie,
Jim Granville
- FPGA MAC for Point to Point Connection, meo2662
- Stratix II - Cyclone II GATE COUNT, vhdldesigner . patrick
- FPGA Full Custum Design,
Midou
- Re: FPGA Full Custum Design, Antti
- Virtex-4 module based partial reconfiguration problem, Pasacco
- Clock signal FPGA XC95288xl144, maroni
- DARNAW! - PGA Style FPGA Module,
John Adair
- Re: DARNAW! - PGA Style FPGA Module,
Symon
- Re: DARNAW! - PGA Style FPGA Module,
John Adair
- Message not available
- Re: DARNAW! - PGA Style FPGA Module, Eric Crabill
- Message not available
- Re: DARNAW! - PGA Style FPGA Module, John Adair
- Re: DARNAW! - PGA Style FPGA Module,
John Adair
- Re: DARNAW! - PGA Style FPGA Module,
Symon
- Re: DARNAW! - PGA Style FPGA Module,
John Adair
- Re: DARNAW! - PGA Style FPGA Module, Eli Hughes
- Re: DARNAW! - PGA Style FPGA Module, John Adair
- Re: DARNAW! - PGA Style FPGA Module, John Adair
- Re: Free Hardware,
Colin Paul Gloster
- Re: Free Hardware,
DJ Delorie
- Re: Free Hardware, Antti
- Re: Free Hardware, Symon
- Re: Free Hardware, Jan Panteltje
- Re: Free Hardware, Symon
- Re: Free Hardware, cs_posting
- Re: Free Hardware, Jan Panteltje
- Re: Free Hardware, Jhoberg
- Re: Free Hardware, Jhoberg
- Re: Free Hardware, Colin Paul Gloster
- Re: Free Hardware, Jhoberg
- Re: Free Hardware, Jhoberg
- Re: Free Hardware, Jhoberg
- Re: Free Hardware, Jhoberg
- Re: Free Hardware, Jhoberg
- Re: Free Hardware, Jhoberg
- Re: Free Hardware, jhobergq
- Re: Free Hardware, Jhoberg
- Re: Free Hardware, Jhoberg
- Re: Free Hardware, Jhoberg
- Re: Free Hardware, Jhoberg
- Re: Free Hardware, Jhoberg
- Re: Free Hardware, Jhoberg
- Re: Free Hardware, Jhoberg
- Re: Free Hardware, Jhoberg
- Re: Free Hardware,
DJ Delorie
- Re: Free Hardware, Jhoberg
- Re: xilprofile for edk 8.2, Paddy
- Re: Spartan 3 IOSTANDARD vs VCCO,
Austin Lesea
- Re: Spartan 3 IOSTANDARD vs VCCO, fsdgsdf
- Re: Regarding drivers for FPGA based PCI cards,
Mark McDougall
- Re: Regarding drivers for FPGA based PCI cards, comp.arch.fpga
- Re: Summer with fpgas,
Austin Lesea
- Re: Summer with fpgas,
cs_posting
- Re: Summer with fpgas, cs_posting
- Re: Summer with fpgas, Kunal
- Re: Summer with fpgas, Mike Harrison
- Re: Summer with fpgas, Austin Lesea
- Re: Summer with fpgas, Eric Brombaugh
- Re: Summer with fpgas, Eric Smith
- Re: Summer with fpgas, Eli Hughes
- Re: Summer with fpgas, cs_posting
- Re: Summer with fpgas, Eli Hughes
- Re: Summer with fpgas,
cs_posting
- Re: Summer with fpgas,
cs_posting
- Re: Summer with fpgas, Steve Battazzo
- Re: Summer with fpgas,
Andreas Ehliar
- Re: Summer with fpgas,
Austin Lesea
- Re: Summer with fpgas, Kunal
- Re: Summer with fpgas, cs_posting
- Re: Summer with fpgas, David M. Palmer
- Re: Summer with fpgas,
Austin Lesea
- Re: Altera M4K memory usage,
Thomas Entner
- Re: Altera M4K memory usage, Manfred Balik
- Re: Problems in simulation (Webpack 9.1.03i),
Duth
- Re: Problems in simulation (Webpack 9.1.03i), Thomas Heller
- Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals., Symon
- Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals., Tim
- Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals., dalai lamah
- Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.,
Peter Alfke
- Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.,
X.Y.
- Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals., Peter Alfke
- Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals., X.Y.
- Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals., Symon
- Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals., X.Y.
- Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals., John_H
- Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.,
X.Y.
- Re: Compiling a library, Duth
- Re: Compiling a library, M. Hamed
- Re: Printing problem with Ise 9.1.03i,
Andy Peters
- Re: Printing problem with Ise 9.1.03i,
nezhate
- Re: Printing problem with Ise 9.1.03i, nezhate
- Re: Printing problem with Ise 9.1.03i, Phil Hays
- Re: Printing problem with Ise 9.1.03i, B. Joshua Rosen
- Re: Printing problem with Ise 9.1.03i, nezhate
- Re: Printing problem with Ise 9.1.03i, Andy Peters
- Re: Printing problem with Ise 9.1.03i,
nezhate
- Re: ISE Smart Ident, Sean Durkin
- Re: ISE Smart Ident, Andy Peters
- Re: BFM simulation and number of Masters?, Mike Lewis
- Re: ModelSim Waveform naming question, backhus
- Re: ModelSim Waveform naming question,
Jonathan Bromley
- Re: ModelSim Waveform naming question,
Andreas Ehliar
- Re: ModelSim Waveform naming question, Andreas Ehliar
- Re: ModelSim Waveform naming question, motty
- ModelSim script for virtual type/function generation, Andreas Ehliar
- Re: ModelSim Waveform naming question,
Andreas Ehliar
- Re: ModelSim Waveform naming question, Kevin Neilson
- Re: Any recommendations for FPGA PCI development board?,
John Adair
- Re: Any recommendations for FPGA PCI development board?, hitsx@xxxxxxxxxx
- Re: Block RAM strange behavior, address off by one,
Gabor
- Re: Block RAM strange behavior, address off by one,
Peter Alfke
- Re: Block RAM strange behavior, address off by one, Newman
- Re: Block RAM strange behavior, address off by one, M. Hamed
- Re: Block RAM strange behavior, address off by one, Peter Alfke
- Re: Block RAM strange behavior, address off by one, M. Hamed
- Re: Block RAM strange behavior, address off by one, Peter Alfke
- Re: Block RAM strange behavior, address off by one, Newman
- Re: Block RAM strange behavior, address off by one, M. Hamed
- Re: Block RAM strange behavior, address off by one, Newman
- Re: Block RAM strange behavior, address off by one, M. Hamed
- Re: Block RAM strange behavior, address off by one,
Peter Alfke
- Re: creating library in ISE 9, Mike Treseler
- Re: creating library in ISE 9, Andy Peters
- 80000 Bit Shift Register - The Code,
Eli Hughes
- Re: 80000 Bit Shift Register - The Code, Frank Buss
- Re: 80000 Bit Shift Register - The Code, Ben Jones
- Re: 80000 Bit Shift Register, Symon
- Re: 80000 Bit Shift Register, Frank Buss
- Re: 80000 Bit Shift Register, Petter Gustad
- Re: 80000 Bit Shift Register, langwadt
- Re: 80000 Bit Shift Register,
HT-Lab
- Re: 80000 Bit Shift Register,
Eli Hughes
- Re: 80000 Bit Shift Register, Eli Hughes
- Re: 80000 Bit Shift Register, Jim Granville
- Re: 80000 Bit Shift Register, Eli Hughes
- Re: 80000 Bit Shift Register, ajjc
- Re: 80000 Bit Shift Register,
Eli Hughes
- Re: No Synplify evaluation?, HT-Lab
- Re: xilinx unused I/O state,
Symon
- Re: xilinx unused I/O state, Symon
- Re: define variable in ISE9.1 Tcl scripts, Andreas Ehliar
- Re: plb_tft_cntlr_ref for an ML405 EDK Project,
Ben Jones
- Re: plb_tft_cntlr_ref for an ML405 EDK Project,
Peter Mendham
- Re: plb_tft_cntlr_ref for an ML405 EDK Project, Ben Jones
- Re: plb_tft_cntlr_ref for an ML405 EDK Project, Peter Mendham
- Re: plb_tft_cntlr_ref for an ML405 EDK Project, Ben Jones
- Re: plb_tft_cntlr_ref for an ML405 EDK Project, Peter Mendham
- Re: plb_tft_cntlr_ref for an ML405 EDK Project,
Peter Mendham
- Re: License Key based on WLAN/Bluetooth MAC,
Uwe Bonnes
- Re: License Key based on WLAN/Bluetooth MAC, Richard Klingler
- Re: License Key based on WLAN/Bluetooth MAC,
Petter Gustad
- Re: License Key based on WLAN/Bluetooth MAC, Gregory C. Read
- Re: License Key based on WLAN/Bluetooth MAC, Richard Klingler
- Re: Safety of bidirectional lines,
Daniel S.
- Re: Safety of bidirectional lines,
Sebastien Bourdeauducq
- Re: Safety of bidirectional lines, Daniel S.
- Re: Safety of bidirectional lines, Symon
- Re: Safety of bidirectional lines, Symon
- Re: Safety of bidirectional lines, Daniel S.
- Re: Safety of bidirectional lines,
Sebastien Bourdeauducq
- Re: Safety of bidirectional lines, Symon
- Re: dual port memory from single port RAM., Tim Wescott
- Re: dual port memory from single port RAM.,
Petter Gustad
- Re: dual port memory from single port RAM.,
vlsi_learner
- Re: dual port memory from single port RAM., Peter Alfke
- Re: dual port memory from single port RAM., vlsi_learner
- Re: dual port memory from single port RAM., vlsi_learner
- Re: dual port memory from single port RAM., vssumesh
- Re: dual port memory from single port RAM., Peter Alfke
- Re: dual port memory from single port RAM.,
vlsi_learner
- Re: dual port memory from single port RAM., Peter Alfke
- Re: Xilinx ISE 9.1,
Georg Acher
- Re: Xilinx ISE 9.1,
Andreas Ehliar
- Re: Xilinx ISE 9.1, Georg Acher
- Re: Xilinx ISE 9.1,
Andreas Ehliar
- Re: Xilinx ISE 9.1,
tullio
- Re: Xilinx ISE 9.1, g . eckersley
- Re: PLB Master,
Ben Jones
- Re: PLB Master,
LilacSkin
- Re: PLB Master, Ben Jones
- Re: PLB Master, LilacSkin
- Re: PLB Master, LilacSkin
- Re: PLB Master,
LilacSkin
- Re: PLB Master,
Eli Hughes
- Re: PLB Master,
Jeff Cunningham
- Re: PLB Master, LilacSkin
- Re: PLB Master, LilacSkin
- Re: PLB Master, Guru
- Re: PLB Master, LilacSkin
- Re: PLB Master, Eli Hughes
- Re: PLB Master, Eli Hughes
- Re: PLB Master, Jeff Cunningham
- Re: PLB Master,
Jeff Cunningham
- Re: vpw/pwm controller,
Jonathan Bromley
- Re: vpw/pwm controller, Martin Thompson
- Re: vpw/pwm controller, ashasravanthi
- Re: How to design a SDIO peripheral card?,
Antti
- Re: How to design a SDIO peripheral card?, Mike Harrison
- Re: OPB To Wishbone Bridge,
jetmarc
- Re: OPB To Wishbone Bridge,
sheikh . m . farhan
- Re: OPB To Wishbone Bridge, sheikh . m . farhan
- Re: OPB To Wishbone Bridge, jetmarc
- Re: OPB To Wishbone Bridge, sheikh . m . farhan
- Re: OPB To Wishbone Bridge,
sheikh . m . farhan
- Re: combinatorial vs sequential, Ralf Hildebrandt
- Re: Running Xilinx 9.1 GUIs on FC6,
g . eckersley
- Re: Running Xilinx 9.1 GUIs on FC6, B. Joshua Rosen
- Re: Running Xilinx 9.1 GUIs on FC6,
Uwe Bonnes
- Re: Running Xilinx 9.1 GUIs on FC6, g . eckersley
- Re: Writing to BRAM using OPB, sovan
- Re: Writing to BRAM using OPB, wsacul@xxxxxxxxx
- Re: Why 166Mhz DDR?,
comp.arch.fpga
- Re: Why 166Mhz DDR?, Benjamin Todd
- Re: Why 166Mhz DDR?, Symon
- Re: Why 166Mhz DDR?,
ghelbig
- Re: Why 166Mhz DDR?,
Daniel S.
- Re: Why 166Mhz DDR?, rohit2000s
- Re: Why 166Mhz DDR?, Daniel S.
- Re: Why 166Mhz DDR?,
Daniel S.
- Re: Why 166Mhz DDR?, Daniel S.
- Re: [xilinx] par [placer] consistency,
Eric Brombaugh
- Re: par [placer] consistency,
mmihai
- Re: par [placer] consistency, mmihai
- Re: par [placer] consistency, Brian Drummond
- Re: par [placer] consistency, Gabor
- Re: par [placer] consistency,
mmihai
- Re: par [placer] consistency, John McGrath
- Re: Pin Count requirements with MICO32,
David M. Palmer
- Re: Pin Count requirements with MICO32, Uwe Bonnes
- Re: ML506 Platform Flash, sovan
- Re: picoblaze C compiler download wanted, -jg
- Re: picoblaze C compiler download wanted,
Nico Coesel
- Re: picoblaze C compiler download wanted, fpga_toys
- Re: picoblaze C compiler download wanted, Eric Smith
- Re: picoblaze C compiler download wanted,
Symon
- Re: picoblaze C compiler download wanted, Eric Smith
- Re: picoblaze C compiler download wanted, Francesco
- Re: SoC, Jonathan Bromley
- Re: Order of the synchronous operations,
Daniel S.
- Re: Order of the synchronous operations,
dalai lamah
- Re: Order of the synchronous operations, Daniel S.
- Re: Order of the synchronous operations, Mike Treseler
- Re: Order of the synchronous operations,
Mike Treseler
- Re: Order of the synchronous operations, dalai lamah
- Re: Order of the synchronous operations, Jonathan Bromley
- Re: Order of the synchronous operations, Mike Treseler
- Re: Order of the synchronous operations, dalai lamah
- Re: Order of the synchronous operations, Mike Treseler
- Re: Order of the synchronous operations, Daniel S.
- Re: Order of the synchronous operations, Jonathan Bromley
- Re: Order of the synchronous operations, Daniel S.
- Re: Order of the synchronous operations, Jonathan Bromley
- Re: Order of the synchronous operations, Daniel S.
- Re: Order of the synchronous operations, Jonathan Bromley
- Re: Order of the synchronous operations, Mike Treseler
- Re: Order of the synchronous operations, Tim
- Re: Order of the synchronous operations, Andy
- Re: Order of the synchronous operations,
dalai lamah
- Re: Order of the synchronous operations, Jonathan Bromley
- Re: JTAG ID code 0xFFFFFFFF, Benjamin Todd
- Re: No login in uClinux (Petalinux), Iwo Mergler
- Re: No login in uClinux (Petalinux), fpga_toys
- Re: Are there Quartus II Web Edition limitations?,
PeterK
- Re: Are there Quartus II Web Edition limitations?,
Maik Ritter
- Re: Are there Quartus II Web Edition limitations?, David Brown
- Re: Are there Quartus II Web Edition limitations?, Maik Ritter
- Re: Are there Quartus II Web Edition limitations?, David Brown
- Re: Are there Quartus II Web Edition limitations?,
Maik Ritter
- Re: Back annotating to RTL, fabbl
- Re: Back annotating to RTL, Andy
- Re: spartan 3e availability,
Austin Lesea
- Re: spartan 3e availability,
emu
- Re: spartan 3e availability, Austin Lesea
- Distributor stock (was Re: spartan 3e availability), Eric Smith
- Re: Distributor stock (was Re: spartan 3e availability), Austin Lesea
- Re: spartan 3e availability,
emu
- Re: SETUP & HOLD time confusion,
Newman
- Re: SETUP & HOLD time confusion,
Peter Alfke
- Re: SETUP & HOLD time confusion, Newman
- Re: SETUP & HOLD time confusion, Symon
- Re: SETUP & HOLD time confusion, Symon
- Re: SETUP & HOLD time confusion, Newman
- Re: SETUP & HOLD time confusion, Symon
- Re: SETUP & HOLD time confusion, M. Hamed
- Re: SETUP & HOLD time confusion, Brian Davis
- Re: SETUP & HOLD time confusion, Peter Alfke
- Re: SETUP & HOLD time confusion,
Peter Alfke
- Re: SETUP & HOLD time confusion, Newman
- Re: how two sine signals are multiplied in VHDL language, Alan Myler \(at home\)
- Re: how two sine signals are multiplied in VHDL language, Alan Nishioka
- Re: Which are the best books about CORDIC algorithms and applications,
Subroto Datta
- Re: Which are the best books about CORDIC algorithms and applications, Weng Tianxiang
- Re: Which are the best books about CORDIC algorithms and applications,
Weng Tianxiang
- Re: Which are the best books about CORDIC algorithms and applications, Ben Jones
- Re: Which are the best books about CORDIC algorithms and applications, Weng Tianxiang
- Re: Which are the best books about CORDIC algorithms and applications, Symon
- Re: Which are the best books about CORDIC algorithms and applications, Jonathan Bromley
- Re: Which are the best books about CORDIC algorithms and applications, Ray Andraka
- Re: Which are the best books about CORDIC algorithms and applications, Jonathan Bromley
- Re: Which are the best books about CORDIC algorithms and applications, Weng Tianxiang
- Re: Which are the best books about CORDIC algorithms and applications, Ray Andraka
- Message not available
- Message not available
- Message not available
- Re: Timing violations though constraints have been met, Mike Treseler
- Re: Timing violations though constraints have been met, Andreas Ehliar
- OT. Re: POC at Element CXI,
Symon
- Re: OT. Re: POC at Element CXI, Gabor
- Re: OT. Re: POC at Element CXI, Mike Treseler
- Message not available
- Re: FIFO newbie question,
nezhate
- Re: FIFO newbie question, comp.arch.fpga
- Re: FIFO newbie question, Gabor
- Re: FIFO newbie question,
nezhate
- Re: Query in Parallel CRC(urgent), Petter Gustad
- Re: Query in Parallel CRC(urgent), Colin Hankins
- Re: Xilinx WebCase support,
Antti
- Re: Xilinx WebCase support,
Helmut
- Re: Xilinx WebCase support, Gabor
- Re: Xilinx WebCase support,
Helmut
- Re: Xilinx WebCase support,
Austin Lesea
- Re: Xilinx WebCase support,
Austin Lesea
- Re: Xilinx WebCase support, motty
- Re: Xilinx WebCase support, Austin Lesea
- Re: Xilinx WebCase support,
Austin Lesea
- Re: CPLD + µC with reasonably-priced tools?, John McCaskill
- Re: CPLD + µC with reasonably-priced tools?,
zcsizmadia@xxxxxxxxx
- Re: CPLD + µC with reasonably-priced tools?,
H. Peter Anvin
- Re: CPLD + µC with reasonably-priced tools?, zcsizmadia@xxxxxxxxx
- Re: CPLD + µC with reasonably-priced tools?, H. Peter Anvin
- Re: CPLD + µC with reasonably-priced tools?, zcsizmadia@xxxxxxxxx
- Re: CPLD + µC with reasonably-priced tools?, Gabor
- Re: CPLD + µC with reasonably-priced tools?,
H. Peter Anvin
- Re: CPLD + µC with reasonably-priced tools?,
-jg
- Re: CPLD + µC with reasonably-priced tools?,
H. Peter Anvin
- Re: CPLD + µC with reasonably-priced tools?, Uwe Bonnes
- Re: CPLD + μC with reasonably-priced tools?, mikeotp999
- Re: CPLD + µC with reasonably-priced tools?,
H. Peter Anvin
- Re: CPLD + µC with reasonably-priced tools?, Symon
- Re: Flip Flop problem (asynchronous or synchronous???? ),
Thomas Stanka
- Re: Flip Flop problem (asynchronous or synchronous???? ), Amine . Miled
- <Possible follow-ups>
- Flip Flop problem (asynchronous or synchronous???? ),
Amine . Miled
- Re: Flip Flop problem (asynchronous or synchronous???? ), Peter Alfke
- Re: Flip Flop problem (asynchronous or synchronous???? ),
Alan Nishioka
- Re: Flip Flop problem (asynchronous or synchronous???? ), Amine . Miled
- Re: Flip Flop problem (asynchronous or synchronous???? ), Austin Lesea
- Re: Flip Flop problem (asynchronous or synchronous???? ), Amine . Miled
- Re: Flip Flop problem (asynchronous or synchronous???? ), Amine . Miled
- Re: Problème de bascues (asynchrone ou synchrone?),
Guy Eschemann
- Re: Problème de bascues (asynchrone ou synchrone?), Amine . Miled
- Re: Ross Freeman - inventor of the FPGA,
Thomas Entner
- Re: Ross Freeman - inventor of the FPGA,
fancier . fpga
- Re: Ross Freeman - inventor of the FPGA, Austin Lesea
- Re: Ross Freeman - inventor of the FPGA, Peter Alfke
- Re: Ross Freeman - inventor of the FPGA,
fancier . fpga
- Re: Ross Freeman - inventor of the FPGA, Bob Perlman
- Re: website for chip designers,
Gabor
- Re: website for chip designers,
art.chipdesign@xxxxxxxxx
- Re: website for chip designers, Scott Willis
- Re: website for chip designers,
art.chipdesign@xxxxxxxxx
- Re: SetJmp/LongJmp for Microblaze, Jon Beniston
- Re: SetJmp/LongJmp for Microblaze, John Williams
- Re: Newbie with bus width mismatch problem. Quartus II, Subroto Datta
- Re: Newbie with bus width mismatch problem. Quartus II, Mark McDougall
- Re: VIrtex-4 FIFO16, Daniel S.
- Re: VIrtex-4 FIFO16, Paul
- Re: MGT Clocking, Ed McGettigan
- Re: Measuring the period of a signal, John_H
- Re: Measuring the period of a signal,
Daniel S.
- Re: Measuring the period of a signal, axr0284
- Re: Measuring the period of a signal, -jg
- Re: Clocking data into a shift register on positive AND negative edges, John_H
- Re: Clocking data into a shift register on positive AND negative edges, Ralf Hildebrandt
- Re: Clocking data into a shift register on positive AND negative edges, Daniel S.
- Re: Clocking data into a shift register on positive AND negative edges, Eric Smith
- <Possible follow-ups>
- Re: Post PAR simulation for RAM Block implementations, veeresh
- Re: raggedstone + xc3sprog?, John Adair
- <Possible follow-ups>
- Nios2: elf2hex settings for epcs bootloader, Dolphin
- Re: Transition from ASIC to FPGA,
Austin Lesea
- Re: Transition from ASIC to FPGA,
From_ASIC_2_FPGA
- Re: Transition from ASIC to FPGA, Ben Twijnstra
- Re: Transition from ASIC to FPGA, John McCaskill
- Re: Transition from ASIC to FPGA, From_ASIC_2_FPGA
- Re: Transition from ASIC to FPGA, Ben Twijnstra
- Re: Transition from ASIC to FPGA, From_ASIC_2_FPGA
- Re: Transition from ASIC to FPGA, Jan Gray
- Re: Transition from ASIC to FPGA, From_ASIC_2_FPGA
- Re: Transition from ASIC to FPGA, Nico Coesel
- Re: Transition from ASIC to FPGA, HT-Lab
- Re: Transition from ASIC to FPGA, Jan Gray
- Re: Transition from ASIC to FPGA,
From_ASIC_2_FPGA
- Re: Transition from ASIC to FPGA, curiousjyo111
- Re: Transition from ASIC to FPGA,
curiousjyo111
- Re: Transition from ASIC to FPGA,
Austin Lesea
- Re: Transition from ASIC to FPGA, From_ASIC_2_FPGA
- Re: Transition from ASIC to FPGA, John_H
- Re: Transition from ASIC to FPGA, From_ASIC_2_FPGA
- Re: Transition from ASIC to FPGA, Tommy Thorn
- Re: Transition from ASIC to FPGA,
Austin Lesea
- Re: PCI FPGA Dev Board Suggestions,
Kunal
- Re: PCI FPGA Dev Board Suggestions,
John Adair
- Re: PCI FPGA Dev Board Suggestions, Kunal
- Re: PCI FPGA Dev Board Suggestions, Nico Coesel
- Re: PCI FPGA Dev Board Suggestions, Nico Coesel
- Re: PCI FPGA Dev Board Suggestions, Vivek Menon
- Re: PCI FPGA Dev Board Suggestions, John Adair
- Re: PCI FPGA Dev Board Suggestions,
John Adair
- Re: PCI FPGA Dev Board Suggestions, evilkidder@xxxxxxxxxxxxxx
- Re: Xilinx ISE webpack in Ubuntu?, zelixor
- Re: suitability of systolic architecture on FPGA, Gabor
- Re: suitability of systolic architecture on FPGA,
Neil Steiner
- Re: suitability of systolic architecture on FPGA,
Peter Alfke
- Re: suitability of systolic architecture on FPGA, Neil Steiner
- Re: suitability of systolic architecture on FPGA,
Peter Alfke
- Re: Gray code in asynchronous FIFO design,
Gabor
- Re: Gray code in asynchronous FIFO design,
anand
- Re: Gray code in asynchronous FIFO design, John_H
- Re: Gray code in asynchronous FIFO design, John_H
- Re: Gray code in asynchronous FIFO design, morpheus
- Re: Gray code in asynchronous FIFO design, Sylvain Munaut
- Re: Gray code in asynchronous FIFO design, morpheus
- Re: Gray code in asynchronous FIFO design, John_H
- Re: Gray code in asynchronous FIFO design, anand
- OT Re: Gray code in asynchronous FIFO design, Symon
- OT Re: Gray code in asynchronous FIFO design, John_H
- Re: OT Re: Gray code in asynchronous FIFO design, Pete Fraser
- Re: OT Re: Gray code in asynchronous FIFO design, John_H
- Re: OT Re: Gray code in asynchronous FIFO design, Symon
- Re: OT Re: Gray code in asynchronous FIFO design, Sylvain Munaut
- Re: OT Re: Gray code in asynchronous FIFO design, Nicolas Matringe
- Re: OT Re: Gray code in asynchronous FIFO design., Symon
- Re: OT Re: Gray code in asynchronous FIFO design., KJ
- Re: Gray code in asynchronous FIFO design,
anand
- Re: Interfacing the DAC0808 to FPGA, Nico Coesel
- Re: Digital Receiver chip suggestion,
Ray Andraka
- Re: Digital Receiver chip suggestion,
morpheus
- Re: Digital Receiver chip suggestion, Ray Andraka
- Re: Digital Receiver chip suggestion,
morpheus
- Re: Digital Receiver chip suggestion,
Marty Ryba
- Re: Digital Receiver chip suggestion, morpheus
- Re: high number of multipliers / low cost, Rob
- Re: high number of multipliers / low cost, Ben Jones
- Re: high number of multipliers / low cost, Sylvain Munaut
- Re: high number of multipliers / low cost,
ryan_usenet
- Re: high number of multipliers / low cost,
Symon
- Re: high number of multipliers / low cost, ryan_usenet
- Re: high number of multipliers / low cost, Ben Jones
- Re: high number of multipliers / low cost, ryan_usenet
- Re: high number of multipliers / low cost, Ben Jones
- Re: high number of multipliers / low cost, Ray Andraka
- Re: high number of multipliers / low cost, Daniel S.
- Re: high number of multipliers / low cost, Ray Andraka
- Re: high number of multipliers / low cost,
Austin Lesea
- Re: high number of multipliers / low cost, ryan_usenet
- Re: high number of multipliers / low cost, Sylvain Munaut
- Re: high number of multipliers / low cost,
Symon
- Re: high number of multipliers / low cost, John_H
- Re: high number of multipliers / low cost, Ray Andraka
- Re: high number of multipliers / low cost, ryan_usenet
- Re: Can I boot PowerPC without JTAG?, John McCaskill
- Re: Conceptos about VCCINT,VCCAUX,etc, jerzy.gbur@xxxxxxxxx
- <Possible follow-ups>
- Re: ModelSim VHDL Pragmas, Ray Andraka
- Re: ModelSim VHDL Pragmas, Ray Andraka
- Re: Spartan 3E Not enough block ram.,
Daniel S.
- Re: Spartan 3E Not enough block ram.,
Ken Soon
- Re: Spartan 3E Not enough block ram., Daniel S.
- Re: Spartan 3E Not enough block ram., Ken Soon
- Re: Spartan 3E Not enough block ram., Daniel S.
- Re: Spartan 3E Not enough block ram., Ken Soon
- Re: Spartan 3E Not enough block ram., Daniel S.
- Re: Spartan 3E Not enough block ram., Ken Soon
- Re: Spartan 3E Not enough block ram., Daniel S.
- Re: Spartan 3E Not enough block ram., Ken Soon
- Re: Spartan 3E Not enough block ram., Daniel S.
- Re: Spartan 3E Not enough block ram., Ken Soon
- Re: Spartan 3E Not enough block ram., Daniel S.
- Re: Spartan 3E Not enough block ram.,
Ken Soon
- Re: Xilinx: WARNING:PhysDesignRules:372 (What the heck?), Benjamin Todd
- Re: Looking for Memory Recommendation for Spartan 3E 1200, John_H
- Re: Looking for Memory Recommendation for Spartan 3E 1200,
John McCaskill
- Re: Looking for Memory Recommendation for Spartan 3E 1200, Matthias Einwag
- Re: Looking for Memory Recommendation for Spartan 3E 1200,
Nico Coesel
- Re: Looking for Memory Recommendation for Spartan 3E 1200, Matthias Einwag
- Re: Looking for Memory Recommendation for Spartan 3E 1200, Paul
- <Possible follow-ups>
- Re: FPGA with 5V and PLCC package,
Jon Elson
- Re: FPGA with 5V and PLCC package, Jim Granville
- Re: FPGA with 5V and PLCC package, Herbert Kleebauer
- Re: FPGA with 5V and PLCC package, Jon Elson
- Re: FPGA with 5V and PLCC package, Jon Elson
- Re: FPGA with 5V and PLCC package, Paul
- Re: Boot PowerPC on VirtexIIPro, Brian Drummond
- Re: Complex Baseband, comp.arch.fpga
- Re: Implement IIR Filter on FPGA,
John_H
- Re: Implement IIR Filter on FPGA,
Gordon Freeman
- Re: Implement IIR Filter on FPGA, Daniel S.
- Re: Implement IIR Filter on FPGA, Gordon Freeman
- Re: Implement IIR Filter on FPGA, Brian Drummond
- Re: Implement IIR Filter on FPGA, Nico Coesel
- Re: Implement IIR Filter on FPGA,
Gordon Freeman
- Re: ISE 9.1i SP3 simulator problems on Linux,
Phil Hays
- Re: ISE 9.1i SP3 simulator problems on Linux,
Andreas Koch
- Re: ISE 9.1i SP3 simulator problems on Linux, Andreas Koch
- Re: ISE 9.1i SP3 simulator problems on Linux,
Andreas Koch
- Re: Does the XC3S250E-VQ100 exist?, Uwe Bonnes
- Re: Does the XC3S250E-VQ100 exist?,
John_H
- Re: Does the XC3S250E-VQ100 exist?,
Paul
- Re: Does the XC3S250E-VQ100 exist?, radarman
- Re: Does the XC3S250E-VQ100 exist?, Uwe Bonnes
- Re: Does the XC3S250E-VQ100 exist?,
Paul
- Re: Dynamic Reconfig, Neil Steiner
- Re: Dynamic Reconfig, prasad . anirudh
- Re: Standard PCI Xilinx board with Ethernet port, John Adair
- Re: verilog genvar, and 2D array access, michel . talon
- <Possible follow-ups>
- Re: Config PROM for Spartan II,
Jon Elson
- Re: Config PROM for Spartan II, Markus Knauss
- <Possible follow-ups>
- Re: Where is Open Source for FPGA development?,
Torsten Landschoff
- Re: Where is Open Source for FPGA development?, comp.arch.fpga
- Re: Where is Open Source for FPGA development?, Stephen Williams
- Re: Where is Open Source for FPGA development?, fpga_toys
- Re: Dear Xilinx,
Benjamin Todd
- Re: Dear Xilinx,
Dave
- Re: Dear Xilinx, rponsard
- Re: Dear Xilinx,
Dave
- Re: Help with a face recognition system,
Islam Ossama
- Re: Help with a face recognition system,
Patrick Dubois
- Re: Help with a face recognition system, Matthew Hicks
- Re: Help with a face recognition system, Patrick Dubois
- Re: Help with a face recognition system, Jan Panteltje
- Re: Help with a face recognition system, Patrick Dubois
- Re: Help with a face recognition system, Jan Panteltje
- Re: Help with a face recognition system, Patrick Dubois
- Re: Help with a face recognition system, Jan Panteltje
- Re: Help with a face recognition system, Patrick Dubois
- Re: Help with a face recognition system,
Patrick Dubois
- Re: broken mb-gcc -O2 ?,
Alan Nishioka
- Re: broken mb-gcc -O2 ?, manuel-lozano
- Re: DCM_STANDBY macro in Virtex-4,
Austin
- Re: DCM_STANDBY macro in Virtex-4,
GaLaKtIkUs™
- Re: DCM_STANDBY macro in Virtex-4, Austin Lesea
- Re: DCM_STANDBY macro in Virtex-4, GaLaKtIkUs™
- Re: DCM_STANDBY macro in Virtex-4,
GaLaKtIkUs™
- <Possible follow-ups>
- Re: ISE on Fedora?,
Günther Jehle
- Re: ISE on Fedora?, M E
- Re: ISE on Fedora?, Eric Smith
