Re: Problem cascading 2 DCMs

On Apr 30, 3:29 pm, Rob Dimond <r...@xxxxxxxxxxxxxxxxxx> wrote:
MNiegl wrote:
Hi everyone,

I have a problem that is bugging me for 2 days now and I was hoping
someone here might be able to help me out.
The problem is as follows:
I want to implement a DDR2 RAM Controller in a Xilinx Virtex 4 FX FPGA
on the Xilinx ML410 eval board. It's supposed to run at 200 MHz, which
I want to derive from the on-board 100 MHz oscillator. For this I need
to use 2 DCMs cascaded (1 to get to 200 MHz, and the second one for
all the other frequencies the RAM controller [generated with MIG 1.6]
needs (main problem is the 200 MHz shifted by 90 deg). The first one
works perfectly fine, only the second one never locks.

[snip]

Hi,

I had all kinds of problems (DCMs not locking was one of them) with MIG
1.6 and a Virtex4FX 100. I'd strongly advise you upgrade to MIG 1.7.

Rob

Hi,

In the meantime I found a work-around using a FX20 as a "clock
generator". I basically just moved the first of the 2 DCMs into the
other FPGA and now feed an LVDS 200 MHz coming from a DCM into the
bigger FPGA. Surprisingly, now the second one immediately locked.
We'll see if the rest of the RAM controller does so as well.
I still might try an update to MIG 1.7, I have just been a bit
reluctant to do so as this would also mean migrating to ISE 9.1 and I
don't want to switch software versions while working on a single
project (which I'm doing since about 8 months now) if not absolutely
necessary. This might be a point where it is absolutely necessary
though.

Cheers,
Michael

.

Relevant Pages

  • Re: Problem cascading 2 DCMs
    ... I have a problem that is bugging me for 2 days now and I was hoping ... I want to implement a DDR2 RAM Controller in a Xilinx Virtex 4 FX FPGA ... I had all kinds of problems with MIG ...
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  • Re: Problem cascading 2 DCMs
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