Re: Problem cascading 2 DCMs



MNiegl wrote:
Hi everyone,

I have a problem that is bugging me for 2 days now and I was hoping
someone here might be able to help me out.
The problem is as follows:
I want to implement a DDR2 RAM Controller in a Xilinx Virtex 4 FX FPGA
on the Xilinx ML410 eval board. It's supposed to run at 200 MHz, which
I want to derive from the on-board 100 MHz oscillator. For this I need
to use 2 DCMs cascaded (1 to get to 200 MHz, and the second one for
all the other frequencies the RAM controller [generated with MIG 1.6]
needs (main problem is the 200 MHz shifted by 90 deg). The first one
works perfectly fine, only the second one never locks.

[snip]

Hi,

I had all kinds of problems (DCMs not locking was one of them) with MIG 1.6 and a Virtex4FX 100. I'd strongly advise you upgrade to MIG 1.7.

Rob
.