Re: TigerSHARC TS201 to PLX 9656

On Apr 29, 1:50 am, Gabor <g...@xxxxxxxxxxx> wrote:
On Apr 28, 4:24 am, eapen.abra...@xxxxxxxxx wrote:

Hi,

Has anyone tried bridging the TS201 TigerSHARC with the PLX 9656
device? I'm trying to implement this in a current project and need
details. The bridging is done via an Altera FPGA which also has to
have custom logic for other functions such as Ethernet, sFPDP,etc.

I know that the TS201 core runs at 600 MHz and the I/O bus at around
83.5 MHz. But at what speed does the PLX 9656 local bus run? Can the
TS201 be connected directly to the PLX chip? Are there anyother
alternatives to the PLX chip?

The PLX9656 has four different local bus modes, but in all
cases the bus is 32-bits wide at 66 MHz max. You should
have no problems meeting the timing with a (recent vintage)
FPGA. You won't be able to directly connect the TigerSHARC
and the PLX9656 unless you get lucky and the bus on the
TS201 matches one of those on the PLX9656 and can
be run at 66 MHz or slower.

Hi,

Thanks for the info. I know that the PLX operates at 66MHz MAX and the
TS201 at 83MHz (I/O). I need to use some asynchronous glue logic to
interface both like an async fifo. The other doubt i had in mind was
with regards to the control lines of the PLX and TS201. The TS201 has
what is called memory banks that are used for memory, I/O accesses.
Have to check up the TS201 read/write cycles and also with the PLX.


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