Re: Placement error for adjacent pins

On Apr 28, 4:51 pm, n...@xxxxxxxxxxx (Nico Coesel) wrote:
Gabor <g...@xxxxxxxxxxx> wrote:
On Apr 27, 5:49 pm, "M. Hamed" <mhs...@xxxxxxxxx> wrote:
I have two pin one is IN and the other is INOUT and they each one goes
to the D input of two FFs clocked by two different clocks Clk1, Clk2.
When I start the PAR process, Xilinx tool complains with the following
error:

ERROR:Place:17 - The placement constraints of the IOBs sck and sdi
makes this design unroutable due to a physical routing limitation.
This device has a shared routing resource connecting the ICLK and
OTCLK pins on pairs of IOBs. This restriction means that these pairs
of pins must be driven by the same signal or one of the signals will
be unroutable. Before continuing please remove the placement
constraints or move one of these IOBs to a new location.

The strange thing is that after looking at the design in the FPGA
editor, IOBs OTCLK are not used at all in the mentioned IOBs and for
one of the pins, the tool is using the internal FFs in the IOB while
in the other it's using only an input buffer and that feeds a FF in
another slice.

Ofcourse removing the pin placement constraint fixes the problem but
that is something that cannot be done for the time being.

I wonder if somebody can help me figure out what's going on.

I'm using ISE 9.1.03i with Spartan 3

Thank you.

You can't change the architecture of the chip. I ran into this same
problem in Virtex 2. Each IOB seems to have two clock inputs that

Afaik each IOB pair in a Spartan 3 has one clock input and a clock
enable (or something like that). Bottom line is, you can use one clock
in an IOB pair.

go to the two clocks of the DDR input and output flip-flops, and
even if you use the same clock for both (rising edge and falling
edge of the same wire) both routing resources are used (wires
from the global routing to the IOB. You have to dig a bit deep in
the data*** to find it, but pairs of IOB's (the same pairs labeled
as "N" and "P" halves of a differential pair) share only two wires
to bring in these two clocks. If both IOB's are using only single

This is definitely not mentioned in the Spartan 3 data***.

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from ds099.pdf:

Some adjacent I/O blocks (IOBs) share common routing
connecting the ICLK1, ICLK2, OTCLK1, and OTCLK2 clock
inputs of both IOBs. These IOB pairs are identified by their
differential pair names IO_LxxN_# and IO_LxxP_#, where
"xx" is an I/O pair number and '#' is an I/O bank number.
Two adjacent IOBs containing DDR registers must share
common clock inputs, otherwise one or more of the clock
signals will be unroutable.

.

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