Re: Placement error for adjacent pins

On Apr 27, 5:49 pm, "M. Hamed" <mhs...@xxxxxxxxx> wrote:
I have two pin one is IN and the other is INOUT and they each one goes
to the D input of two FFs clocked by two different clocks Clk1, Clk2.
When I start the PAR process, Xilinx tool complains with the following
error:

ERROR:Place:17 - The placement constraints of the IOBs sck and sdi
makes this design unroutable due to a physical routing limitation.
This device has a shared routing resource connecting the ICLK and
OTCLK pins on pairs of IOBs. This restriction means that these pairs
of pins must be driven by the same signal or one of the signals will
be unroutable. Before continuing please remove the placement
constraints or move one of these IOBs to a new location.

The strange thing is that after looking at the design in the FPGA
editor, IOBs OTCLK are not used at all in the mentioned IOBs and for
one of the pins, the tool is using the internal FFs in the IOB while
in the other it's using only an input buffer and that feeds a FF in
another slice.

Ofcourse removing the pin placement constraint fixes the problem but
that is something that cannot be done for the time being.

I wonder if somebody can help me figure out what's going on.

I'm using ISE 9.1.03i with Spartan 3

Thank you.


You can't change the architecture of the chip. I ran into this same
problem in Virtex 2. Each IOB seems to have two clock inputs that
go to the two clocks of the DDR input and output flip-flops, and
even if you use the same clock for both (rising edge and falling
edge of the same wire) both routing resources are used (wires
from the global routing to the IOB. You have to dig a bit deep in
the data*** to find it, but pairs of IOB's (the same pairs labeled
as "N" and "P" halves of a differential pair) share only two wires
to bring in these two clocks. If both IOB's are using only single
data rate flip-flops, the two wires allow them to be pretty much
independent of eachother. However when at least one has
DDR flip-flops, the two IOB's need to share clock routing. Thus
in a DDR SDRAM design for example you can't place a DQ
pin and a DQS pin in two halves of a differential pair.

The synthesis tool has apparently worked around this issue
in your case by using fabric flip-flops for one of the two IOB's.
If you can't change the pin location in your current design,
the best you can do is to LOC the fabric slice where these
flip-flops will end up. In the package pin listings from Xilinx
there is a column showing the location of the nearest (from
a routing perspective) slice to each IOB.

HTH,
Gabor

PS read the section in the data*** (ds099) titled
"Double-Data-Rate Transmission" in the IOBs functional
description. This is p. 13 in my copy which may
not be the latest version. The paragraph starting
"Some adjacent I/O blocks . . ." describes this.

.

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