Is there a reset signal available in verilog in Xilinx FPGAs?
- From: janbeck@xxxxxxxxx
- Date: 27 Apr 2007 15:47:54 -0700
As a sample here is some code. To be clear: I am not looking for
alternate ways to code the following always block; I would like to
know a way to access the power on reset from verilog. The block is
just a simple example of where a reset might be used. I am aware that
flip flops in an fpga get initialized globally upon power up.
reg faultReg3;
always @ (posedge slow_clk)
if (reset) faultReg3 <= 0;
else if (fault3) faultReg3 <= 1;
else faultReg3 <= faultReg3;
.
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