Re: suitability of systolic architecture on FPGA
- From: "Peter Alfke" <peter@xxxxxxxxxx>
- Date: 5 Apr 2007 15:07:04 -0700
Neil, we all have to live in the real world.
If you think of something that needs 10,000 I/O, then it is time to
start thinking differently. Usually there are many ways to "skin a
cat".
I remember when 16 pins were the norm, and 40 pins was the max. But we
can now give you almost a thousand usable I/O in BGAs, with no fear of
accidentally bending the pins.
But let's not go too much further, otherwise the pc-board design
becomes worse than a nightmare.
Ultra-high speed serial communication looks more extendable,
especially once we learn to put the electrical-to-optical (and vice
vers) transducers on the chip...
Peter Alfke
==================
On Apr 5, 10:37 am, Neil Steiner <neil.stei...@xxxxxx> wrote:
I understand that because of the 2d array CLB structure of FPGA,
systolic architecture can be mapped efficiently into FPGA. however,
what about the high IO ports requirements. if the outputs need to be
stored in the memory, all the achieved speed will be lost due to the
limited off chip ram bandwith [especially if using one bank]. so why
this architecture is widely used in matrix algorithms implementation.
The excessive I/O bandwidth requirement will surely dent the expected
high clocking frequency
You are entirely correct. There are all kinds of designs where the
memory and IO bandwidths are not a problem, but there are other cases
where those limitations can reduce the FPGA to a relatively small amount
of logic that spends most of its time starved for data.
Those are the times when you try to keep a straight face and explain to
Xilinx that you really do need 10,000 IO to keep the device busy (a true
story from Los Alamos), or when you start considering completely
different approaches, preferably with the help of one of the consultants
who frequent this forum.
.
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