Re: high number of multipliers / low cost
- From: Ray Andraka <ray@xxxxxxxxxxx>
- Date: Wed, 04 Apr 2007 15:25:01 -0400
ryan_usenet@xxxxxxxxx wrote:
Hello,
I need the highest possible number of multiplication operations per
second at low cost. I know that several factors affect the overall
performance, but since I have no idea which FPGA chips might be worth
to be considered, I'd like to ask what you think is the chip with the
lowest ratio
R=(prize of chip)* (delay time)/(number of multipliers)
18x18bit multipliers seem to be quite common, so lets assume this
design for the estimate.
For example for the Spartan XC3S1000 (~60$, 24 multipliers, 4ns delay)
I have
R= 10$ per (Billion multiplications/s). The Cyclone EP2C70 (~230$, 150
multipliers, 4ns delay) has R=6.13$ per (Billion multiplications/s).
Do other FPGAs exist that are maybe specialized for multiplication-
intensive tasks and which therefore are much cheaper?
Best regards,
Ryan
What is your application? There is usually more than one way to approach a problem. For example, distributed arithmetic is an elegant solution to handling a sum of products with constant or nearly constant coefficients that does a great job at compacting the area required for fabric multipliers. The precipitation radar design on my website gallery ( http://www.andraka.com/precip_radar.htm ) does about 82 multiply-accumulates per clock cycle at 133 MHz, which works out to over 10 billion multiplies/sec in an FPGA that has zero hardware multipliers (XCV1000) and is rather small and slow compared to current FPGA offerings. In order to find a possible alternative approach, you need to disect your algorithm to see if there are other constructs that might get you the performance you want in a reasonable amount of hardware.
.
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