Re: high number of multipliers / low cost

Symon wrote:

<ryan_usenet@xxxxxxxxx> wrote in message news:1175696938.323383.273760@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

Although your suggestions have already been useful, I'd appreciate
more hints maybe concerning exotic manufacturers that I have never
heard of. Or are Xilinx and Altera definitely the only choices?

Best regards,
Ryan


Hi Ryan,
Don't forget FPGAs have other resources apart from 'hard' multipliers. Check this page on Mr. Andraka'a website about distributed arithmetic. You can make a _lot_ of multipliers out of the ordinary fabric of FPGAs.
HTH, Syms.

http://www.andraka.com/distribu.htm


You can also time-share the multipliers. The DSP48 elements in Virtex 4 can be clocked at 400 MHz in the slow speed grade part. With careful design, the fabric can also support 400 MHz (well, except for the carry logic, which is hard pressed at 400MHz for anything but simple counters). My gigasample floating point FFT design runs on a 400 MHz clock in a V4SX55. That design is highlighted in this month's Xilinx DSP magazine: http://www.xilinx.com/publications/magazines/dsp_03/xc_pdf/p42-44-3dsp-andraka.pdf
and I have the floorplan for that design on my website at http://www.andraka.com/V4_FP_fft.htm
.

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