Re: Help with a face recognition system

Peter,

First of all, thanks for replying :-).

We (team of 5) spent the last semester exploring and evaluating the
different algorithms. We came to the conclusion that PCA would be the
best compromise between complexity and accuracy, with the
recommendation that Neural Networks be added into it if possible, to
increase the accuracy even further.

We did evaluate different implementations of the algorithm, some on
MATLAB and some running natively, and the performance was as we
expected: not suitable for real-time, especially for large face
databases.

This only confirmed what was suggested at the beginning of our
research, which was the main reason we wanted to explore an FPGA
implementation to make up for the performance shortcomings while
maintaining (or better, increasing) the level of accuracy.

Right now we have in fact divided up the work between us, and 3 of my
team are working on the algorithm (it being the main focus of the
project), while one is working on the neural network, and myself
working on the FPGA.

What remains to be determined is the kind of design that the algorithm
will be implemented with. Whether it would be solely VHDL, a soft
microprocessor and asm/C/C++ code, or some combination of the two.
And, of course, whether the hardware currently at hand would support
that design.

Also, after sending my earlier post, I stumbled upon a project on
opencores.org called Java Optimized Processor (http://
www.opencores.com/projects.cgi/web/jop/overview), which is essentially
a soft processor for Java bytecode. I was wondering how good/robust/
flexible it is, and whether someone here has actually used it in any
way on actual hardware. I might try to implement it and download it to
my FPGA, if I can get it to compile on Webpack 9.1i without trouble.

I did check out the Xilinx University Program. The "Virtex-II Pro
Development System" seems like an extreme overkill in our case, since
the use of FPGA isn't standard curriculum in our faculty; we are
mainly doing this as a unique, single-case approach. It seems like an
excellent choice for an engineering faculty, though. Unfortunately, I
don't think our faculty (Computer Science) would be willing to make
such a purchase based on a single case requirement, especially taking
into account the relatively high currency exchange rate (1 USD ~= 5.7
EGP).

Thanks again for your response, and I hope I haven't bored you with my
long reply...

Best Regards,
Islam Ossama

On Mar 31, 5:17 am, "Peter Alfke" <a...@xxxxxxxxxxxxx> wrote:
Islam,
If I were you, I would:
first explore the best algorithm
then see whether it can be implemented on a (any!) microprocessor,
achieving reasonable performance.
If the microprocessor implementation is too slow, I would look at a
way to speed it up with an FPGA, and I would use an existing board of
reasonable performance.
The Xilinx University Program has a better board, based on Virtex-
IIPro, that is surprisingly inexpensive for universities.
I would contact the Xilinx University Program about details.

Challenging project!
Peter Alfke

.

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