Re: ModelSim VHDL Pragmas

Gabor wrote:
On Mar 30, 4:11 pm, "Andy Peters" <goo...@xxxxxxxxx> wrote:
On Mar 30, 12:00 pm, "Peter Klemperer" <ftpe...@xxxxxxxxx> wrote:

Hi All,
In one of my VHDL designs I have a section of code that I want
different versions for synthesis than for simulation. Currently I
just comment out one section and uncomment the other, but I had a
rather embarassing incident yesterday where I forgot to change the
comments before beginning synthesis. Ooops.
I searched around a bit, but haven't found a definitive solution other
than using a preprocessor. I don't think that this is a satisfactory
solution. Eliminating the simulation only code is simple, the --
synthesis translate_off/on pragmas works great. Is there an
equivalent for modelsim?
Generate statements?

-a


That's a solution to reducing the changes needed, but it doesn't fully
automate the changes unless there's a way to detect which compiler is
being used - Modelsim or synthesis. If you had a way to put your
synthesis-specific code at the top of the file, you could use the -
line
option for vcom in Modelsim to start compilation after the synthesis
only section, but I don't see this as very practical. If you were
using Verilog I could think of a few ways to deal with this...
In Verilog for example you can define a macro on the command line
and then use `ifdef `else to exclude code that is for synthesis only.

Depending on the extent of your optional code, can you use two different architectures, & a configuration file to choose between them?
.

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