Re: RISC implementation questions


You can certainly alias onto any 'do nothing single cycle opcode' which
may have been what Austin was meaning ?

The problem is as follows: I have got two write ports to the register
file. In my architecture I have two execution units, a memory access
unit and
a multiplier. So in the worst case scenario, it could happen that all
these four units want to write to the regfile. This causes a
structural hazard as I only
have two write ports. My question is now whats the best way to deal
with this situation? My approach was, that if OP = 0, the alu stage
outputs a signal
to the writeback stage that there is no meaningful outport available
and I dont need the write port. So instead of having a NOP that writes
in the WB stage 0
into R0 I just use an additional control signal so that the WB stage
doesnt use the write port and it would be available for the memory
access pipeline for instance.
So either the alu output should be written back or the memory access
uses the writeport. I have to make sure that not both of the units
want
to access the same write port in the same clock cycle. Is this okay to
handle this with additional control signals or is there another way to
do that? Or can I use
here some kind kind of resolved signal where either the the output of
the alu or the output of the memory access unit determines the value
to be written?


.

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