Re: Problems with Xilinx Parallel III Cable
- From: "John_H" <newsgroup@xxxxxxxxxxxxxxxx>
- Date: Thu, 29 Mar 2007 13:26:52 -0700
<EvalXX@xxxxxxxxx> wrote in message
news:1175195472.611147.280310@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
On Mar 28, 6:55 pm, "John_H" <newsgr...@xxxxxxxxxxxxxxxx> wrote:
<jid...@xxxxxxxxxxx> wrote in message
news:1175098335.158323.203250@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
The newer Xilinx programming cables (Parallel Cable IV, Platform Cable
USB)
use comparators rather than simple buffers to establish proper voltage
Where can I get these kind of comparators? What about multiple
voltages? Any sample circuits I can use as a reference?
Thanks
- E.
Almost any kind of comparators?
Take a look at the Platform Cable USB Product Specification
http://direct.xilinx.com/bvdocs/publications/ds300.pdf
pages 11-12 for an idea what Xilinx does to get the voltage compliance and
well-defined threshold values. If you substitute the 5V LPT buffers for the
CPLD, you can pretty much cut & paste your way from a Parallel-III to a
Parallel-IV style cable (though you'd still refer to it in SW as a
Paralell-III).
I should reiterate that having your VCC act as both a VREF and source for a
DC-DC converter is a solid way to design for the 5V LPT interface and the
lower-voltage JTAG interface.
.
- References:
- Problems with Xilinx Parallel III Cable
- From: jidan1
- Re: Problems with Xilinx Parallel III Cable
- From: John_H
- Re: Problems with Xilinx Parallel III Cable
- From: EvalXX
- Problems with Xilinx Parallel III Cable
- Prev by Date: Re: suggestion for choosing the right FPGA for gigabit transciever
- Next by Date: Re: FPGA with 5V and PLCC package
- Previous by thread: Re: Problems with Xilinx Parallel III Cable
- Next by thread: Re: Problems with Xilinx Parallel III Cable
- Index(es):
Relevant Pages
|
