Re: Confuse on Spartan speed

Yes, aiming for fmax is an exercise in extreme pipelining and is unlikely to do any good for one's sanity but as impractical as it may be, it is possible to do it for real designs... it just gets costly (consume FFs for routing and sacrifice LUTs), ugly (lots of code that does nothing except move data along) and inconvenient (more tricky/complex control logic) pretty quickly.

Paul wrote:
As stated here.... for ANY fpga, the specified Fmax is a theoretical
max. Odds are you will never hit that if you are doing anything
vaguely complex. That assumes your logic as pipelined to the maximum
capabilities of the part - no more than one LUT of combinatorial logic
before a DFF - so it makes maximum use of the CLB layout. It also
assumes that routing delays are near negligible - i.e. assumes your
design can be routed such that you flow from one CLB directly to the
neiboring CLB. As soon as you go through more than one LUT of
combinatorial logic before a flop or pack your part tight enough that
your routes aren't all COMPLETELY ideal.... that is to say, as soon
as you put a real design in the part, that Fmax goes down depending
upon the details of your design.
.