Re: suggestion for choosing the right FPGA for gigabit transciever
- From: "John_H" <newsgroup@xxxxxxxxxxxxxxxx>
- Date: Wed, 28 Mar 2007 14:16:15 -0700
"vasile" <piclist9@xxxxxxxxx> wrote in message
news:1175110434.467891.112950@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Hi,
I need to chose between the Altera Stratix II GX or Stratix III GX and
some Xilinx Virtex5 FPGA for an implementation of gigabit interface
into a multi DSP system.
Could you suggest pro and cons between Altera and Xilinx (or maybe
others) for such design ?
If I'm trying to compare Altera with Xilinx FPGA based on those
websites, both are telling is better than the other.
Maybe you know and independent comparison table between those two ?
thank you,
Vasile
Do you need the raw power and size of those devices or do you long for
something more cost effective do do generic workhorse processing at decent
speeds and sizes? If so, consider the Lattice ECP2M series as well. They
may also have the lowest power transceivers in the industry:
Lattice:
3.125Gbps Embedded SERDES (ECP2M only)
Low 100mW power per channel
Xilinx:
Flexible SERDES with 100 Mbps-to-3.2 Gbps operating range supports all
popular protocols
Lowest power consumption in the industry: less than 100 mW per channel
at 3.2 Gbps
(shall we say 99.99 mW?)
The Lattice devices may not be fancy. They are used in quads rather than
trying to divide the functionality into smaller increments. But if what you
need is the raw bandwidth without super-extreme processing in between,
consider the outsider.
In my opinion, the ECP2M product has given Lattice a strong leg up on the
competition for a strong range of price/performance devices.
The points that are imprtant to some may not be important to others. Are
you concerned with:
Power? (Is >100 mW a problem?)
Speed? (Is 3.125Gb/s enough?)
Cost? (Whoa)
Flexibility? (How much granularity? # of independent channels? Channel
width?)
Device size? (How many LEs/LUTs will you need? RAM?)
Multiplier/DSPblock functionality? (Are there features that tip the
balance)
Logic speed? (Do you need 200 MHz or 500 MHz? Simple or complex paths?)
Clocking? (Do the devices support your clock source cleanly?)
I haven't seen a good apples-to-apples comparison becasue these choices and
concerns tend to make analysis less obvious.
- John_H
.
- Follow-Ups:
- References:
- Prev by Date: Re: Problems with Xilinx Parallel III Cable
- Next by Date: Re: Problems with Xilinx Parallel III Cable
- Previous by thread: Re: suggestion for choosing the right FPGA for gigabit transciever
- Next by thread: Re: suggestion for choosing the right FPGA for gigabit transciever
- Index(es):
Relevant Pages
|