Re: Problems with Xilinx Parallel III Cable

On 28 Mrz., 22:30, jid...@xxxxxxxxxxx wrote:
On 28 Mrz., 21:16, Duane Clark <junkm...@xxxxxxxxxxxx> wrote:



jid...@xxxxxxxxxxx wrote:

I used 3.3V JTAG interface since the beginning, and also since the
beginning I had problems with it. I think part of the problem might be
in the buffer itself. The input voltage at the buffer(74HC125) used
there, according to the data ***, should be max. VCC+1.5. And if you
are using VCC=3.3V or 2.5V, the high level voltage coming from the
LPT(5V) will be exceeding the max. input voltage. A series resistor
was used to limit the current going through the clamp didoe, however
the signal might have got distorted because of that.I have also
thought about using Schmitt-triggers instead of buffers. At the end I
built the exact circuit posted in xilinx website, because I thought
the Xilinx team knows better than me. But that circuit has caused me a
lot of problems and it seems I am not the only one!

I've always stuck two (because they are inverting) 74HCT14 Schmidt
triggers in there, and have no problems with long parallel cables on a
number of different boards and computers.

May I ask why you used inverting and not non-inverting schmitt-
triggers? I assume if you used inverting schmitt-triggers you would
have to change the programmer software to allow these inverted signals
to be understandable.

JJ

....or did you actually mean you used two inverted schitt-triggers
becuase you didn't have one non-inverted schmitt-trigger :)

.