Re: FPGA with 5V and PLCC package

Herbert Kleebauer wrote:

Jim Granville wrote:


What are the prime teaching targets: learning FPGA flows, or
learning shematic entry ?


Nothing of both. The goal is, to use a handful of FlipFlops and
gates to implement a design for which you only get the specification.
It's just a replacement for a prototyping board with many TTL gates.

OK, I understand why you want to keep as much 'visible' as possible.



Isn't '5 years old', actually new on your time scales ?
Get the Atmel tools and try them


Atmel only offers a place and route tool. Therefore I asked if
somebody can suggest a simple to use design software (with
a schematic entry) for the Atmel FPGA's.


- has anybody experience with ATMEL's AT40K20 and can suggest
development software (it must be a schematic entry, no VHDL
because the students have to "see" the processor at gate level.

What about simpler HDLs, like CUPL or ABEL ?
With those, you can 'see' the AND and OR terms ?
What about 'seeing' the result in the report files - is that
gate-level enough ?


That's like a city map which doesn't use graphics but only
textual description of the street position and connections.
You will never get a feeling for the layout of the city
whereas a fast glance on the graphical city map shows you
all. Sure, if you use one of the modern navigation systems
you don't need any overview of the city, you are told
when to turn left or right. This may be is the best way
if you only want to go from position A to position B,
but if have to understand how the city is organized, then
this is completely inappropriate.

Yes, I can follow this SCH thrust, only to a point, so let's look more
closely :

In your Doc, there is a nice block diagram, on page 3.
That's what I used, [and I note it is not actually from Viewlogic]

So, you certainly keep that.

but if I drill down, to your ALU example, I can see 16 blocks, but
they are still macros, and I need to drill further to ADDNOR.

Now, ask the student : "Quick, how many macrocells will the ALU need
in device AAX ? "

Next, look at YGATE or YREG, and in both HDL, and SCH I'd call that
pretty much a tie.

YReg.d = Din;
YReg.ck = CLK;
YReg.ce = s2;

should be clear to anyone, as a CE DFF ?

Next, look at the state engine - and this is where SCH fails badly.
I would not try and duplicate your design from the GATES on p10, but
I would either use the table you give on page 4, and probably paste that
into a CUPL table statement, or I'd use the Boolean equations you have
provided on page 4, and code using those, or I could use a Sequence
state construct.
With state engines, I prefer to make it readable.maintainable, and let the tools do the packing - they are tricky things, and clarity is
important.

Another advantage of HDL/Boolean eqn entry, is the student WILL have
to read the FIT reports, and the equations in those are ? - yes, boolean Eqns. So, it is faster/easier to jump between Source in editor, and report, in the same editor, than Source in SCH XYZ, and report in separate editor.

Source Code:

YReg.d = Din;
YReg.ck = CLK;
YReg.ce = s2;

YGate = s6 & YReg
# !s6 & 'h'0001;


FIT report

YReg0.C = CLK;
YReg0.CE = s2;
YReg0.D = Din0;

!YGate0 = (!YReg0.Q & s6); /* student exercise: what/why has the fitter done this ? */

I spend a significant portion of design time looking at the FIT reports, and I also frequently use multiple constructs, and pick the best one.

$IFDEF VesionCom
Code = here # there;
$ELSE
Code.d = here # there;
$ENDIF

Try that in Viewlogic ? :)

Then we come to tool control: I can feed commands to the fitter, from CUPL source, - how do you do that from Viewlogic ?

Simulation ?: Also in the same editor. How do you enter/view simulation
data, with Viewlogic ?





2. Was somebody able to run Viewlogic (DOS version) in a virtual
PC emulation. The problem is, the virtual PC must provide
the proper graphics mode, mouse type and support a physical
dongle on the virtual parallel port.

Keys on virtual parallel ports ?! Nope...

Then it should be legal to remove the copy protection from
the software.

I thought it almost was, in this type of case, in the EU ?

-jg

.

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