Re: Initialization of arrays in Verilog

Hi!

* "Uwe Bonnes" <bon@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:
Till Wollenberg <till@xxxxxxxxxxxx> wrote:
...
But now I have to synthesize the design using ISE 7.1i...

Tell us why you have to synthesize with 7.1i

Updating to 8.1i would surely solve my problem but I don't have
appropriate permissions and so I'm stuck with 7.1i at least for
the next days.

I thought that there *must* be a way to initialize arrays with
7.1i. Googling a bit I found some discussion threads exactly covering
my problem but they all end up without a solution.

Till.

--
real e-mail: wollenberg (at) web (dot) de

.

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