Re: Large power planes vs. power islands vs. slits for decoupling
- From: sweir@xxxxxxx
- Date: 6 Mar 2007 14:56:37 -0800
Symon, you are welcome. An out of office junk filter is mandatory for
SI-List sanity.
Intel has been doing what you mention for a long time. The cut-off
frequency between the PCB and package is down in the low MHz, and
falling. For all of those other chips, the keys to good decoupling
are: low inductance, low inductance, and low inductance. That is why
I like X2Y's so much and consult for X2Y. Six vias with one X2Y will
get you 100pH at the surface + 4-5pH / mil for plunge down to the
power cavity. Only IDC caps come close with similar numbers for eight
vias. Resonance management is a matter of managing phase. That too
means getting low inductance.
I have long been fascinated with the Proadlizers but have never found
a situation where I felt they were the best answer. They are (or
were ) pricey, big and need a lot of vias. I have always found I
could synthesize a cheaper solution with cheaper capacitors, sometimes
a little creative etch, and in the very rare instance a little iron.
The FPGA guys have an interesting set of trade-offs to resolve. They
tend to use power pins for signal return path as well as power
distribution. They also don't get to choose return path of things
like DDR2 memory, which is Vss for data and Vccio for address /
control. As edge rates continue to push upwards, this gets trickier
to manage.
Regards,
Steve.
On Mar 6, 3:20 am, "Symon" <symon_bre...@xxxxxxxxxxx> wrote:
<s...@xxxxxxx> wrote in message
news:1173137413.433634.222140@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> In the PS3
application, those mighty ASICs have a lot of bypass under the lid.
From a system design perspective this is cheaper than trying to makethe PCB do all the work. The PCB just becomes a low frequency power
distribution network. Since Sony isn't asking the PCB to distribute
high frequency, using the Proadlizers to isolate noise is an effective
way to limit EMI propagation. That allows meeting FCC with thicker
dielectric in the power planes of the PCB.
Regards,
Steve.
Hi Steve,
Firstly, thanks for your post. I lurk on the SI-list (posting is a pain with
all those 'out-of-office' replies) which is how I found your stuff onX2Y.
The paragraph of yours I've quoted above explains to me what's going on
inside a PS3. For a while I was worrying that I'd missed a big trick with my
FPGA board designs. If FPGA manufacturers follow this lead of putting even
more bypassing on the BGA carrier, and I guess that soon they will have no
choice, then the PCB power distribution requirements will become a little
less rigorous.
Thanks again, Symon.
.
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