Re: Multiplication operation

Peter, I totally agree with your points and while writing my post I knew there would be a huge difference in perspective because of one, the generation(s) gap, as I am still in graduate school, and two, the background, as I have a C.S. degree. However, my comments were more for beginners who shouldn't be overloaded in the infinite amounts of complexity possible with FPGAs (for an example just read one of Austin's posts). Newbies who are probably working on some trivial project should get the fundamentals first (everything is binary, data flow, ...) and then work towards the actual optimized implementations gradually building in complexity, if constraints deem it necessary. After all, you don't learn to swim in the ocean during a hurricane, you start in the kiddy pool.

Although, I still believe a lot of work needs to be done to synthesis engines so they can better abstract the low-level complexity away from the designer all the while resulting in an optimized implementation. For a quick example, I still cannot believe you don't optimize across files during synthesis. For the time being, I prefer the embedded systems point of view presented in Dave's response.


---Matthew Hicks


Matthew let me argue for peace:
It all depends on your roots.
If you started out as a logic designer (like I did), then you see the
FPGA as a wonderful way to design a production-worthy breadboard of
terrific complexity and very good performance. God's gift to the logic
designer, good-bye wire-wrap!
I think in terms of block diagrams, and use VHDL/Verilog to manage the
design process. I would never be in doubt about the choice of binary
vs decimal, or fixed vs floating point, because they have such
enenormous impact on the design efficiency.
If you start out as a computer programmer, then you design=program the
way this thread was started, totally oblivious of hardware constraints
and limittions. Let the synthesizer worry about those details! The
trouble is that these unworthy details can impact the design by an
order of magnitude in size=cost and performance.

You will never beat the urge for economy, performance, and design
elegance out of us hardware guys. Maybe one day FPGAs will become so
big and cheap and fast that it does not matter anymore.
Well, hopefully there will always be Social Security.
And St. Peter might show mercy with us former pip-pokers genus
schemato-saurus.
Peter Alfke
On Mar 4, 12:12 pm, Matthew Hicks <mdhic...@xxxxxxxx> wrote:

First, to address the question, you're not really doing
multiplication but
performing division through multiplication with decimals. ISE
doesn't do
division either way. Like John_H said, scale your numbers up (refer
to fixed
point numbers) so multiplication is done with integers. When done,
just
scale the result down by the same amount for the final answer. A
hint is
to scale the numbers by a power of 2 so you just have to do bit
shifts.
Second, I would like to give my two cents on John_H's 1990's
attitude. You
shouldn't tell someone to read up on vendor specific blocks when it
is clear
that they are just starting out, doesn't need an optimal
implementation,
and don't have a firm grasp on the basics. You should give them a
very simple
and concise explanation at their level and a fix at their level. The
synthesizer
is more than capable of handling the * symbol, the OP doesn't need to
worry
about what Xilinx puts on the hood. If Xilinx were smart and had
good programmers,
which it seems they are trying to work towards, no one would need to
know
of any of the blocks under the hood. People should be able to
"program"
the hardware. The synthesis program should be smart enough to use
the blocks
under the hood to provide a near optimal implementation of the
"program".
There is a reason why people use high level programming languages not
assembly.
For everyone's sake, "designing" a system on an FPGA shouldn't be
hard.
---Matthew Hicks

VHDL_HELP wrote:

Hi every body ,
i hope that you can help me , i want to do this operation:
s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1
when i check the syntax , i have these errors
ERROR:HDLParsers:808 - "C:/Xilinx/projet/operation.vhd" Line 44. *
can
not have such operands in this context.
-------------------------------------------------------------------
--
-------------------------------------------------------------------
--
----------------------
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity operation is
Port ( clk : in STD_LOGIC;
c1 : in STD_LOGIC_VECTOR (7 downto 0);
c2 : in STD_LOGIC_VECTOR (7 downto 0);
c 3: in STD_LOGIC_VECTOR (7 downto 0);
s: out STD_LOGIC_VECTOR (7 downto 0);
end operation;
architecture Behavioral of operation is

begin

s <=c1 * 0.2 + c2 * 0.6 + c3 * 0.1 ;

end Behavioral;

-------------------------------------------------------------------
--
-------------------------------------------------------------------
-- ----------------

and thanks for your help

Can you tell me how the synthesizer will format your floating point
result in s so it maps to silicon?

Use scaled integers. Use the precision available in the hardware
multipliers to get a rather precise approximation of s. The digital
realm is binary, after all, not decimal.

Please read up on how the hardware multipliers perform and how best
to utilize them. It's insanely sad to see someone trying to
"program" an FPGA rather than design it.



.

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