comp.arch.fpga

• Date Index

---

• microblaze bootloader, yash . r . modi
• ISE on Fedora?, M E
• Config PROM for Spartan II, Markus Knauss
• Static RAM implementation with VHDL, zahra . lak
  • <Possible follow-ups>
  • Static RAM implementation with VHDL, zahra . lak
• Help with a face recognition system, Islam Ossama
  • Re: Help with a face recognition system, Peter Alfke
    • Re: Help with a face recognition system, Islam Ossama
      • Re: Help with a face recognition system, Jim Granville
      • Re: Help with a face recognition system, Matthew Hicks
      • Re: Help with a face recognition system, Islam Ossama
      • Re: Help with a face recognition system, Peter Alfke
      • Re: Help with a face recognition system, Islam Ossama
• Sysgen compilation target, mans
• Another simple DCM question, lecroy7200@xxxxxxxx
  • Re: Another simple DCM question, Gabor
    • Re: Another simple DCM question, Austin Lesea
      • Re: Another simple DCM question, Gabor
• ModelSim VHDL Pragmas, Peter Klemperer
  • Re: ModelSim VHDL Pragmas, Andy Peters
    • Re: ModelSim VHDL Pragmas, Gabor
      • Re: ModelSim VHDL Pragmas, David R Brooks
      • Re: ModelSim VHDL Pragmas, Peter Klemperer
  • Re: ModelSim VHDL Pragmas, Tim
    • Re: ModelSim VHDL Pragmas, John McCaskill
• EDP 2007 (Power and DFM Focus) -- Early Registration Ends 03/31/07, b_kapoor
• Xilkernel-EDK8.2, olive_dominguez
  • <Possible follow-ups>
  • Xilkernel-EDK8.2, olive_dominguez
  • Xilkernel-EDK8.2, olive_dominguez
• xilinx ise/edk/modelsim - what does compilation really do?, Brad Parker
  • Re: xilinx ise/edk/modelsim - what does compilation really do?, Gabor
    • Re: xilinx ise/edk/modelsim - what does compilation really do?, David R Brooks
• Complex Baseband, morpheus
  • Re: Complex Baseband, John McCaskill
    • Re: Complex Baseband, morpheus
      • Re: Complex Baseband, morpheus
      • Re: Complex Baseband, Symon
  • Re: Complex Baseband, comp.arch.fpga
    • Re: Complex Baseband, morpheus
      • Re: Complex Baseband, Symon
  • Re: Complex Baseband, Ray Andraka
    • Re: Complex Baseband, morpheus
• "undeclared here" error and undesired file persistance in Xilinx Platform Studio, Tom J
  • Re: "undeclared here" error and undesired file persistance in Xilinx Platform Studio, John McCaskill
    • Re: "undeclared here" error and undesired file persistance in Xilinx Platform Studio, Tom J
• Webpack 9.1 Service Pack 3, Uwe Bonnes
  • Re: Webpack 9.1 Service Pack 3, davide
  • Re: Webpack 9.1 Service Pack 3, davide
• Regarding connecting two Ethernet Mac Phy, Adnan
  • Re: Regarding connecting two Ethernet Mac Phy, zcsizmadia@xxxxxxxxx
• We need avnet fx12 mini module URGENTLY!, ricardo . ribalda
• Some errors i dont know in XMD, fouRmi
• Watershed Transform, Pablo
  • Re: Watershed Transform, Brian Drummond
• suggestion for choosing the right FPGA for gigabit transciever, vasile
  • Re: suggestion for choosing the right FPGA for gigabit transciever, Austin Lesea
  • Re: suggestion for choosing the right FPGA for gigabit transciever, John_H
    • Re: suggestion for choosing the right FPGA for gigabit transciever, lb . edc
      • Re: suggestion for choosing the right FPGA for gigabit transciever, John_H
  • Re: suggestion for choosing the right FPGA for gigabit transciever, Karl
• Problems with Xilinx Parallel III Cable, jidan1
  • Re: Problems with Xilinx Parallel III Cable, zcsizmadia@xxxxxxxxx
    • Re: Problems with Xilinx Parallel III Cable, jidan1
  • Re: Problems with Xilinx Parallel III Cable, John_H
    • Re: Problems with Xilinx Parallel III Cable, jidan1
      • Re: Problems with Xilinx Parallel III Cable, Duane Clark
      • Re: Problems with Xilinx Parallel III Cable, jidan1
      • Re: Problems with Xilinx Parallel III Cable, jidan1
      • Re: Problems with Xilinx Parallel III Cable, Duane Clark
      • Re: Problems with Xilinx Parallel III Cable, jidan1
      • Re: Problems with Xilinx Parallel III Cable, Duane Clark
      • Re: Problems with Xilinx Parallel III Cable, jidan1
      • Re: Problems with Xilinx Parallel III Cable, John_H
      • Re: Problems with Xilinx Parallel III Cable, jidan1
    • Re: Problems with Xilinx Parallel III Cable, EvalXX
      • Re: Problems with Xilinx Parallel III Cable, John_H
  • Re: Problems with Xilinx Parallel III Cable, comp.arch.fpga
    • Re: Problems with Xilinx Parallel III Cable, jidan1
  • Re: Problems with Xilinx Parallel III Cable, Peter Wallace
    • Re: Problems with Xilinx Parallel III Cable, Uwe Bonnes
    • Re: Problems with Xilinx Parallel III Cable, jidan1
• Compiling simulation libraries of EDK 8.1.02i under Linux, dtheodor
• Confuse on Spartan speed, Ace
  • Re: Confuse on Spartan speed, Andreas Ehliar
    • Re: Confuse on Spartan speed, Paul
      • Re: Confuse on Spartan speed, Ace
      • Re: Confuse on Spartan speed, Daniel S.
      • Re: Confuse on Spartan speed, Ace
      • Re: Confuse on Spartan speed, Daniel S.
• is edk 8.1 availabe for download, mahalingamv@xxxxxxxxx
  • Re: is edk 8.1 availabe for download, Ace
• OT. Given and family names., Symon
• What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L, Weng Tianxiang
  • Re: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L, John_H
    • Re: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L, Weng Tianxiang
      • Re: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L, Peter Alfke
      • Re: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L, Paul Leventis
      • Re: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L, Weng Tianxiang
      • Re: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L, Weng Tianxiang
      • Re: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L, Peter Alfke
• longest webcase record, Jason
• (Xilinx) OPB watchdog timer fails to release RESET, radarman
  • Re: (Xilinx) OPB watchdog timer fails to release RESET, Alan Nishioka
  • Re: (Xilinx) OPB watchdog timer fails to release RESET, Brian Drummond
  • Re: (Xilinx) OPB watchdog timer fails to release RESET, Alan Nishioka
    • Re: (Xilinx) OPB watchdog timer fails to release RESET, radarman
• Help with Xilinx Parallel Cable IV., Pete Fraser
  • Re: Help with Xilinx Parallel Cable IV., Sean Durkin
    • Re: Help with Xilinx Parallel Cable IV., Pete Fraser
      • Re: Help with Xilinx Parallel Cable IV., Andreas Ehliar
      • Re: Help with Xilinx Parallel Cable IV., Daniel O'Connor
      • Re: Help with Xilinx Parallel Cable IV., Andreas Ehliar
      • Re: Help with Xilinx Parallel Cable IV., Daniel O'Connor
  • Re: Help with Xilinx Parallel Cable IV., Zara
• Lattice "Open IP" license is GPL-compatible?, jonas
  • Re: Lattice "Open IP" license is GPL-compatible?, Daniel S.
    • Re: Lattice "Open IP" license is GPL-compatible?, Jim Granville
    • Re: Lattice "Open IP" license is GPL-compatible?, Andreas Ehliar
      • Re: Lattice "Open IP" license is GPL-compatible?, jonas
• Re: EDK : Import Custom Peripheral, Andrew Dupont
• PCI-Express drivers with Xilinx FPGA?, eromlignod
  • Re: PCI-Express drivers with Xilinx FPGA?, Joseph Samson
    • Re: PCI-Express drivers with Xilinx FPGA?, eromlignod
  • Re: PCI-Express drivers with Xilinx FPGA?, John_H
    • Re: PCI-Express drivers with Xilinx FPGA?, eromlignod
      • Re: PCI-Express drivers with Xilinx FPGA?, John_H
  • Re: PCI-Express drivers with Xilinx FPGA?, Colin Hankins
    • Re: PCI-Express drivers with Xilinx FPGA?, eromlignod
• CycloneII altlvds_rx, Dolphin
  • Re: CycloneII altlvds_rx, Rob
    • Re: CycloneII altlvds_rx, Dolphin
      • Re: CycloneII altlvds_rx, Rob
      • Re: CycloneII altlvds_rx, Dolphin
      • Re: CycloneII altlvds_rx, Rob
      • Re: CycloneII altlvds_rx, Ben Twijnstra
• Where is MIG 1.7???, GaLaKtIkUs™
  • Re: Where is MIG 1.7???, Helmut
  • Re: Where is MIG 1.7???, GaLaKtIkUs™
    • Re: Where is MIG 1.7???, Helmut
• FPGA board with multiple Ethernet connections (Gigabit Ethernet), sheikh . m . farhan
  • <Possible follow-ups>
  • FPGA board with multiple Ethernet connections (Gigabit Ethernet), sheikh . m . farhan
    • Re: FPGA board with multiple Ethernet connections (Gigabit Ethernet), comp.arch.fpga
• Post PAR simulation for RAM Block implementations, veeresh
  • Re: Post PAR simulation for RAM Block implementations, Duth
  • <Possible follow-ups>
  • Post PAR simulation for RAM Block implementations, veeresh
• No results show up after "dow" and "con" in hypertrm, fouRmi
• Spartan 3E Not enough block ram., Ken Soon
  • Re: Spartan 3E Not enough block ram., Paul
  • Re: Spartan 3E Not enough block ram., Daniel S.
    • Re: Spartan 3E Not enough block ram., Ken Soon
      • Re: Spartan 3E Not enough block ram., Daniel S.
• RISC implementation questions, Patrick
  • Re: RISC implementation questions, Jan Gray
    • Re: RISC implementation questions, Patrick
      • Re: RISC implementation questions, Jan Gray
  • Re: RISC implementation questions, Andreas Hofmann
    • Re: RISC implementation questions, Patrick
      • Re: RISC implementation questions, Austin Lesea
      • Re: RISC implementation questions, Jim Granville
      • Re: RISC implementation questions, Patrick
      • Re: RISC implementation questions, Jim Granville
      • Re: RISC implementation questions, Patrick
      • Re: RISC implementation questions, Ben Jones
      • Re: RISC implementation questions, Patrick
      • Re: RISC implementation questions, Peter Y
      • Re: RISC implementation questions, Patrick
      • Re: RISC implementation questions, Daniel S.
      • Re: RISC implementation questions, Austin Lesea
  • Re: RISC implementation questions, Ben Popoola
• Minimal pins for JTAG configuration, jidan1
  • Re: Minimal pins for JTAG configuration, Austin Lesea
    • Re: Minimal pins for JTAG configuration, jidan1
      • Re: Minimal pins for JTAG configuration, Austin Lesea
      • Re: Minimal pins for JTAG configuration, jidan1
      • Re: Minimal pins for JTAG configuration, Austin Lesea
      • Re: Minimal pins for JTAG configuration, jidan1
      • Re: Minimal pins for JTAG configuration, Austin Lesea
• how to read a sequence of video, kha_vhdl
  • Re: how to read a sequence of video, John_H
    • Re: how to read a sequence of video, John_H
  • Re: how to read a sequence of video, Peter Alfke
    • Re: how to read a sequence of video, Mark McDougall
  • Re: how to read a sequence of video, Eric Smith
    • Re: how to read a sequence of video, kha_vhdl
      • Re: how to read a sequence of video, Guenter
      • Re: how to read a sequence of video, John_H
      • Re: how to read a sequence of video, kha_vhdl
• Quartus warning messages reagarding timming and latchs, djoshi
  • Re: Quartus warning messages reagarding timming and latchs, vbetz
• Re: Delta Sigma A/D's integrated in FPGA's, Symon
• Small memories in Cyclone, MikeF
  • Re: Small memories in Cyclone, Mike Treseler
  • Re: Small memories in Cyclone, Paul Leventis
    • Re: Small memories in Cyclone, John_H
• Re: help needed, djoshi
  • Re: help needed, djoshi
    • Re: help needed, Rob
  • Re: help needed, Rob
  • <Possible follow-ups>
  • Re: help needed, djoshi
• Where is Open Source for FPGA development?, psihodelia
  • Re: Where is Open Source for FPGA development?, Jim Granville
    • Re: Where is Open Source for FPGA development?, Daniel S.
      • Re: Where is Open Source for FPGA development?, Jim Granville
    • Re: Where is Open Source for FPGA development?, comp.arch.fpga
      • Re: Where is Open Source for FPGA development?, Colin Paul Gloster
  • Re: Where is Open Source for FPGA development?, Ben Jones
  • Re: Where is Open Source for FPGA development?, David Brown
    • Re: Where is Open Source for FPGA development?, Jan Panteltje
      • Re: Where is Open Source for FPGA development?, David Brown
  • Re: Where is Open Source for FPGA development?, Symon
  • Re: Where is Open Source for FPGA development?, Guenter
  • Re: Where is Open Source for FPGA development?, Eric Smith
    • Re: Where is Open Source for FPGA development?, Daniel S.
      • Re: Where is Open Source for FPGA development?, Eric Smith
      • Re: Where is Open Source for FPGA development?, Daniel S.
      • Re: Where is Open Source for FPGA development?, Andy Peters
      • Re: Where is Open Source for FPGA development?, Daniel S.
      • Re: Where is Open Source for FPGA development?, comp.arch.fpga
      • Re: Where is Open Source for FPGA development?, Martin Thompson
      • Re: Where is Open Source for FPGA development?, Daniel S.
      • Re: Where is Open Source for FPGA development?, Martin Thompson
      • Re: Where is Open Source for FPGA development?, Daniel S.
      • Re: Where is Open Source for FPGA development?, Martin Thompson
      • Re: Where is Open Source for FPGA development?, Daniel S.
      • Re: Where is Open Source for FPGA development?, Colin Paul Gloster
  • Re: Where is Open Source for FPGA development?, Andy Peters
• Tool to convert ISE project into makefile? (for Linux), Wojciech Zabolotny
  • Re: Tool to convert ISE project into makefile? (for Linux), Andreas Ehliar
  • Re: Tool to convert ISE project into makefile? (for Linux), Dave Vanden Bout
• Altera memory init file (.hex/.mif) generation using gcc objcopy - how to change base address??, Edmond Coté
  • Re: Altera memory init file (.hex/.mif) generation using gcc objcopy - how to change base address??, vbetz
• convertion real to std_logic_vector, kha_vhdl
  • Re: convertion real to std_logic_vector, Eric Smith
    • Re: convertion real to std_logic_vector, kha_vhdl
• shift register with distributed ram, CMOS
  • <Possible follow-ups>
  • shift register with distributed ram, CMOS
    • Re: shift register with distributed ram, John McCaskill
    • Re: shift register with distributed ram, Peter Alfke
      • Re: shift register with distributed ram, John McCaskill
      • Re: shift register with distributed ram, Marty Ryba
      • Re: shift register with distributed ram, John_H
      • Re: shift register with distributed ram, Peter Alfke
      • Variable delay line (was Re: shift register with distributed ram), Marty Ryba
      • Re: Variable delay line (was Re: shift register with distributed ram), Peter Alfke
      • Re: shift register with distributed ram, Ray Andraka
      • Re: shift register with distributed ram, Peter Alfke
    • Re: shift register with distributed ram, John_H
• Re: OPB IPIF: write to DIER causing bus timeout, Neil Steiner
• Solaris 10, Michael Laajanen
  • Re: Solaris 10, navanee
• Amphion IP MPEG2 Video DecoderCores, amitpatel130
• iMPACT:CRC Error bit is NOT 0, toanfxt
• EDK and Custom Peripheral: error occur when generating bitstream, Allen
  • Re: EDK and Custom Peripheral: error occur when generating bitstream, Zara
    • Re: EDK and Custom Peripheral: error occur when generating bitstream, Allen
      • Re: EDK and Custom Peripheral: error occur when generating bitstream, John McCaskill
      • Re: EDK and Custom Peripheral: error occur when generating bitstream, Allen
      • Re: EDK and Custom Peripheral: error occur when generating bitstream, Allen
      • Re: EDK and Custom Peripheral: error occur when generating bitstream, John McCaskill
• Custom IP ports to be used as GPIOs, Sandip
  • Re: Custom IP ports to be used as GPIOs, MM
• Flash memmory model, vssumesh
  • Re: Flash memmory model, Gabor
    • Re: Flash memmory model, vssumesh
• problem while using if or case statements, ravipativishnu
  • Re: problem while using if or case statements, Joseph Samson
• IEEE 802.3 Ethernet MAC implemetation in FPGA, ritesh
  • Re: IEEE 802.3 Ethernet MAC implemetation in FPGA, Symon
• multiple clock domain issues, JK
  • Re: multiple clock domain issues, Thomas Stanka
  • Re: multiple clock domain issues, Daniel S.
    • Re: multiple clock domain issues, JK
• Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF, mwiesbock
  • Re: Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF, mwiesbock
    • Re: Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF, MM
      • Re: Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF, mwiesbock
    • Re: Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF, Jim Wu
      • Re: Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF, mwiesbock
• Parallel Cable IV in Spartan 3E???, Pablo
  • Re: Parallel Cable IV in Spartan 3E???, Benjamin Todd
  • Re: Parallel Cable IV in Spartan 3E???, John_H
    • Re: Parallel Cable IV in Spartan 3E???, Pablo
      • Re: Parallel Cable IV in Spartan 3E???, John_H
      • Re: Parallel Cable IV in Spartan 3E???, Pablo
• Matrix inversion in FPGA, nsrsn
• CRC check error, Xuan Binh
  • Re: CRC check error, devb
• Digital AM/FM Receiver - Systemic Question, morpheus
  • Re: Digital AM/FM Receiver - Systemic Question, Ben Twijnstra
• Re: Need fair opinions on choosing either Altera or Xilinx as main FPGA source, lnds
• Looking for resources on timing analysis, FPGAEngineer@xxxxxxxxx
  • Re: Looking for resources on timing analysis, Eric Crabill
    • Re: Looking for resources on timing analysis, FPGAEngineer@xxxxxxxxx
      • Re: Looking for resources on timing analysis, Eric Crabill
      • Re: Looking for resources on timing analysis, morpheus
• Manual LUT - AND function mapping problem, Pasacco
  • Re: Manual LUT - AND function mapping problem, John_H
  • Re: Manual LUT - AND function mapping problem, Jim Wu
• how to shift mutiple bytes in an array in one clock cycle?, CMOS
  • Re: how to shift mutiple bytes in an array in one clock cycle?, John_H
• gated clock, patrick . melet
  • Re: gated clock, Symon
    • Re: gated clock, patrick . melet
      • Re: gated clock, Symon
      • Re: gated clock, patrick . melet
      • Re: gated clock, Symon
  • Re: gated clock, dkarchmer
• LZW compression and decompression in vhdl, eric
  • Re: LZW compression and decompression in vhdl, John_H
• CPLD erase??, mtsukanov
  • Message not available
    • Re: CPLD erase??, Eric Smith
      • Re: CPLD erase??, mtsukanov
• How to generate STAPL with "pulse PROG" in Impact?, Wojciech Zabolotny
  • SOLVED: How to generate STAPL with "pulse PROG" in Impact?, Wojciech Zabolotny
• Data width in Block ram, ZHI
  • Re: Data width in Block ram, Daniel S.
    • Re: Data width in Block ram, ZHI
      • Re: Data width in Block ram, Daniel S.
  • Re: Data width in Block ram, Brad Smallridge
    • Re: Data width in Block ram, ZHI
• Re: OFFSET and Data Clock Skew?, kislo
• How to make use of two processors with Xilinx ISE (on Linux), Wojciech Zabolotny
  • Re: How to make use of two processors with Xilinx ISE (on Linux), Petter Gustad
• Austin the Altera Mole, rickystickyrick
  • Re: Austin the Altera Mole, Derek Simmons
    • Re: Austin the Altera Mole, KJ
      • Re: Austin the Altera Mole, Paul Leventis
      • Re: Austin the Altera Mole, rickystickyrick
      • Re: Austin the Altera Mole, Austin Lesea
      • Re: Austin the Altera Mole, Paul
      • Re: Austin the Altera Mole, John_H
      • Re: Austin the Altera Mole, Andy Peters
      • Re: Austin the Altera Mole, dalai lamah
      • Re: Austin the Altera Mole, fpgabuilder
      • Re: Austin the Altera Mole, Paul
      • Re: Austin the Altera Mole, fpgabuilder
      • Re: Austin the Altera Mole, Paul Leventis
      • Re: Software Management, Austin Lesea
      • Re: Austin the Altera Mole, fpgabuilder
• how to make a matlab simulink wave into mif or hex form., kangwei365@xxxxxxxxx
• Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?, Marc Randolph
  • Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?, Fred
    • Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?, David Brown
• Why is Xilinx's WebPACK so inferior?, Taylor Hutt
  • Re: Why is Xilinx's WebPACK so inferior?, Symon
  • Re: Why is Xilinx's WebPACK so inferior?, Jim Granville
  • Re: Why is Xilinx's WebPACK so inferior?, Austin
    • Re: Why is Xilinx's WebPACK so inferior?, Austin
    • Re: Why is Xilinx's WebPACK so inferior?, jonas
      • Re: Why is Xilinx's WebPACK so inferior?, mikeandmax
    • Re: Why is Xilinx's WebPACK so inferior?, Jim Granville
      • Off topic: what is the purpoe of XST?, Austin
      • Re: Off topic: what is the purpoe of XST?, Jim Granville
      • Re: Off topic: what is the purpoe of XST?, cs_posting
      • Re: Off topic: what is the purpoe of XST?, Thomas Entner
      • Re: Off topic: what is the purpoe of XST?, Austin Lesea
      • Re: Off topic: what is the purpoe of XST?, Jim Granville
      • Re: Off topic: what is the purpoe of XST?, John_H
      • XST coverage, Austin Lesea
      • Re: XST coverage, none
      • Re: XST coverage, HT-Lab
      • Re: XST coverage, Austin Lesea
      • Re: Off topic: what is the purpoe of XST?, Daniel S.
      • Re: Off topic: what is the purpoe of XST?, Tim
      • Re: Off topic: what is the purpoe of XST?, MM
      • Re: Off topic: what is the purpoe of XST?, cs_posting
      • Re: Off topic: what is the purpoe of XST?, steve.lass
      • Re: Off topic: what is the purpoe of XST?, Jim Granville
      • Re: Off topic: what is the purpoe of XST?, steve.lass
      • Re: Off topic: what is the purpoe of XST?, MM
      • Re: Off topic: what is the purpoe of XST?, doug
      • Re: Off topic: what is the purpoe of XST?, steve.lass
      • Re: Off topic: what is the purpoe of XST?, jonas
      • Re: Off topic: what is the purpoe of XST?, MM
      • Re: Off topic: what is the purpoe of XST?, Jim Granville
      • Re: Off topic: what is the purpoe of XST?, steve.lass
      • Re: Off topic: what is the purpoe of XST?, doug
      • Re: Off topic: what is the purpoe of XST?, Thomas Entner
      • Re: Off topic: what is the purpoe of XST?, MM
    • Re: Why is Xilinx's WebPACK so inferior?, Mike Harrison
  • Re: Why is Xilinx's WebPACK so inferior?, Tommy Thorn
    • Re: Why is Xilinx's WebPACK so inferior?, Austin
      • Re: Why is Xilinx's WebPACK so inferior?, Tommy Thorn
      • Re: Why is Xilinx's WebPACK so inferior?, Austin Lesea
    • Re: Why is Xilinx's WebPACK so inferior?, Daniel S.
      • Re: Why is Xilinx's WebPACK so inferior?, Andy Peters
  • Re: Why is Xilinx's WebPACK so inferior?, Nico Coesel
  • Re: Why is Xilinx's WebPACK so inferior?, MM
    • Re: Why is Xilinx's WebPACK so inferior?, Austin Lesea
    • Re: Why is Xilinx's WebPACK so inferior?, Taylor Hutt
      • Re: Why is Xilinx's WebPACK so inferior?, John_H
      • Re: Why is Xilinx's WebPACK so inferior?, Taylor Hutt
      • Re: Why is Xilinx's WebPACK so inferior?, davide
    • Re: Why is Xilinx's WebPACK so inferior?, Jeff Cunningham
• Virtex-II block RAM problem, dimtey
  • Re: Virtex-II block RAM problem, Peter Alfke
  • Re: Virtex-II block RAM problem, Peter Alfke
    • Re: Virtex-II block RAM problem, Dmitry Teytelman
  • Re: Virtex-II block RAM problem, Duane Clark
    • Re: Virtex-II block RAM problem, Dmitry Teytelman
      • Re: Virtex-II block RAM problem, John_H
      • Re: Virtex-II block RAM problem, Dmitry Teytelman
      • Re: Virtex-II block RAM problem, Daniel S.
      • Re: Virtex-II block RAM problem, Dmitry Teytelman
      • Re: Virtex-II block RAM problem, Martin Thompson
      • Re: Virtex-II block RAM problem, John_H
      • Re: Virtex-II block RAM problem, Dmitry Teytelman
      • Re: Virtex-II block RAM problem, Martin Thompson
      • Re: Virtex-II block RAM problem, Daniel S.
      • Re: Virtex-II block RAM problem, Duane Clark
      • Re: Virtex-II block RAM problem, Duane Clark
• Zero-Valued Data Out of Chipscope ILA?, Brandon Jasionowski
  • Re: Zero-Valued Data Out of Chipscope ILA?, Symon
  • Re: Zero-Valued Data Out of Chipscope ILA?, Ben Jackson
• Re: Unable to load FPGA image from the prom, brian . magnusen
• 1.8V config proms for Cyclone 2s, fpgabuilder
• softcore CPU tools, InmateRemo
  • Re: softcore CPU tools, Austin Lesea
    • Re: softcore CPU tools, David Brown
  • Re: softcore CPU tools, Göran Bilski
  • Re: softcore CPU tools, Jim Granville
    • Re: softcore CPU tools, RemisN
      • Re: softcore CPU tools, Jim Granville
      • Re: softcore CPU tools, joerg
      • Re: softcore CPU tools, RemisN
      • Re: softcore CPU tools, joerg
      • Re: softcore CPU tools, RemisN
  • Re: softcore CPU tools, Eric
    • Re: softcore CPU tools, Jon Beniston
• FF's are inffered instead of distributed RAM, CMOS
  • Re: FF's are inffered instead of distributed RAM, Andy Peters
  • Re: FF's are inffered instead of distributed RAM, Andy
• Using xilkernel with C++, Guy Eschemann
  • Re: Using xilkernel with C++, Markus
    • Re: Using xilkernel with C++, Guy Eschemann
• FPGA with 5V and PLCC package, Herbert Kleebauer
  • Re: FPGA with 5V and PLCC package, msg
    • Re: FPGA with 5V and PLCC package, Herbert Kleebauer
    • Re: FPGA with 5V and PLCC package, Herbert Kleebauer
  • Re: FPGA with 5V and PLCC package, Symon
    • Re: FPGA with 5V and PLCC package, Herbert Kleebauer
      • Re: FPGA with 5V and PLCC package, cs_posting
      • Re: FPGA with 5V and PLCC package, Herbert Kleebauer
      • Re: FPGA with 5V and PLCC package, cs_posting
      • Re: FPGA with 5V and PLCC package, glen herrmannsfeldt
      • Re: FPGA with 5V and PLCC package, Jim Granville
      • Re: FPGA with 5V and PLCC package, Jim Granville
      • Re: FPGA with 5V and PLCC package, glen herrmannsfeldt
  • Re: FPGA with 5V and PLCC package, cs_posting
    • Re: FPGA with 5V and PLCC package, Herbert Kleebauer
      • Re: FPGA with 5V and PLCC package, cs_posting
  • Re: FPGA with 5V and PLCC package, Jim Granville
    • Re: FPGA with 5V and PLCC package, Herbert Kleebauer
      • Re: FPGA with 5V and PLCC package, cs_posting
      • Re: FPGA with 5V and PLCC package, Jim Granville
      • Re: FPGA with 5V and PLCC package, Jim Granville
      • Re: FPGA with 5V and PLCC package, glen herrmannsfeldt
      • Re: FPGA with 5V and PLCC package, jetmarc
  • Re: FPGA with 5V and PLCC package, John Adair
    • Re: FPGA with 5V and PLCC package, Herbert Kleebauer
      • Re: FPGA with 5V and PLCC package, John Adair
  • Re: FPGA with 5V and PLCC package, Jim Granville
    • Re: FPGA with 5V and PLCC package, Herbert Kleebauer
      • Re: FPGA with 5V and PLCC package, Benjamin Todd
      • Re: FPGA with 5V and PLCC package, cs_posting
      • Re: FPGA with 5V and PLCC package, Jim Granville
      • Re: FPGA with 5V and PLCC package, glen herrmannsfeldt
  • Re: FPGA with 5V and PLCC package, Herbert Kleebauer
    • Re: FPGA with 5V and PLCC package, Symon
      • Re: FPGA with 5V and PLCC package, Herbert Kleebauer
      • Re: FPGA with 5V and PLCC package, Jim Granville
• Automatically adding pcore from XBD (Xilinx Board Definition) file?, Torsten Landschoff
• prog_b held low?, mtsukanov
  • Re: prog_b held low?, mtsukanov
    • Re: prog_b held low?, mtsukanov
      • Re: prog_b held low?, mtsukanov
• timing in xilinx fpga, Ruzica
  • Re: timing in xilinx fpga, Andreas Ehliar
    • Re: timing in xilinx fpga, Ruzica
      • Re: timing in xilinx fpga, Austin Lesea
  • Re: timing in xilinx fpga, Symon
    • Re: timing in xilinx fpga, Ruzica
      • Re: timing in xilinx fpga, Symon
      • Re: timing in xilinx fpga, Ruzica
  • Re: timing in xilinx fpga, John_H
• create test bench of video, kha_vhdl
  • Re: create test bench of video, Paul
    • Re: create test bench of video, kha_vhdl
• Wanted: container classes for reconfigurable computing, acd
• Xilinx ISE Inferred block rams, dlharmon
  • Re: Xilinx ISE Inferred block rams, John_H
    • Re: Xilinx ISE Inferred block rams, Gabor
      • Re: Xilinx ISE Inferred block rams, John_H
    • Re: Xilinx ISE Inferred block rams, dlharmon
• Sparten 3E clock generator, T-Mike
  • Re: Sparten 3E clock generator, Peter Alfke
• ModelSim PE exit code 211, Markus
  • Re: ModelSim PE exit code 211, HT-Lab
    • Re: ModelSim PE exit code 211, Markus
• Altera introduces Cyclone III devices, ships 65nm, lschirrm
  • Re: Altera introduces Cyclone III devices, ships 65nm, -jg
  • Re: Altera introduces Cyclone III devices, ships 65nm, Uwe Bonnes
  • Re: Altera introduces Cyclone III devices, ships 65nm, Jim Granville
    • Re: Altera introduces Cyclone III devices, ships 65nm, lschirrm
  • Re: Altera introduces Cyclone III devices, ships 65nm, Austin
    • Re: Altera introduces Cyclone III devices, ships 65nm, Rob
    • Re: Altera introduces Cyclone III devices, ships 65nm, -jg
    • Re: Altera introduces Cyclone III devices, ships 65nm, John_H
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Austin Lesea
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, John_H
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Austin Lesea
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Paul Leventis
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Austin Lesea
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Paul Leventis
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Paul Leventis
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Austin Lesea
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Paul Leventis
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, John_H
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Paul Leventis
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Austin Lesea
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Paul Leventis
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Austin Lesea
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Paul Leventis
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Austin Lesea
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Jim Granville
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, John_H
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Paul Leventis
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Tim
      • Re: Altera introduces Cyclone III devices, 'ships' 65nm, Austin Lesea
• a project work, jd
  • Re: a project work, John_H
  • Re: a project work, Remis Norvilis
• direct access on opb_emc, cpope
  • Re: direct access on opb_emc, cpope
• Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*, Duth
• QuickSilver's ACM architecture, Anne
• IOSTANDARD default value in Xilinx UCF-Files?, Torsten Landschoff
  • Re: IOSTANDARD default value in Xilinx UCF-Files?, Joseph Samson
    • Re: IOSTANDARD default value in Xilinx UCF-Files?, Torsten Landschoff
      • Re: IOSTANDARD default value in Xilinx UCF-Files?, Joseph Samson
  • Re: IOSTANDARD default value in Xilinx UCF-Files?, bwilson79@xxxxxxxxx
    • Re: IOSTANDARD default value in Xilinx UCF-Files?, Marc Randolph
• Jam STAPL Player extensions, Wojciech Zabolotny
  • Re: Jam STAPL Player extensions, cs_posting
    • Re: Jam STAPL Player extensions, wzab
      • Re: Jam STAPL Player extensions, cs_posting
      • Re: Jam STAPL Player extensions, wzab
• ADC capture with FPGA Spartan3 in Verilg, Jhoberg
• FPGA vs. GPP anyone?, yasirmm
  • Re: FPGA vs. GPP anyone?, Peter Alfke
    • Re: FPGA vs. GPP anyone?, Ben Jackson
      • Re: FPGA vs. GPP anyone?, Phil Hays
    • Re: FPGA vs. GPP anyone?, Ace
      • Re: FPGA vs. GPP anyone?, comp.arch.fpga
      • Re: FPGA vs. GPP anyone?, glen herrmannsfeldt
• CFP : FPL 2007 (Submission deadline extended to 25th of March), David Thomas
• How to find pcore directory from within EDK TCL script?, John McCaskill
• Eval board advice, elr
  • Re: Eval board advice, John Adair
    • Re: DDR2 and SDRAM modules for Raggedstone 1, Thomas Glanzmann
      • Re: DDR2 and SDRAM modules for Raggedstone 1, John Adair
  • Re: Eval board advice, Daniel S.
    • Re: Eval board advice, Rivas
      • Re: Eval board advice, Daniel S.
      • Re: Eval board advice (+DDR2/SDRAM modules for Raggedstone), Rivas
      • Re: Eval board advice, John Adair
• XPower crashes...., Xesium
  • Re: XPower crashes...., Xesium
• Xilinx ISE support for dual/quad core CPUs?, Patrick Dubois
  • Re: Xilinx ISE support for dual/quad core CPUs?, Daniel S.
    • Re: Xilinx ISE support for dual/quad core CPUs?, Patrick Dubois
      • Re: Xilinx ISE support for dual/quad core CPUs?, B. Joshua Rosen
      • Re: Xilinx ISE support for dual/quad core CPUs?, Patrick Dubois
      • Re: Xilinx ISE support for dual/quad core CPUs?, General Schvantzkoph
      • Re: Xilinx ISE support for dual/quad core CPUs?, Patrick Dubois
      • Re: Xilinx ISE support for dual/quad core CPUs?, Ray Andraka
      • Re: Xilinx ISE support for dual/quad core CPUs?, Daniel S.
      • Re: Xilinx ISE support for dual/quad core CPUs?, Patrick Dubois
  • Re: Xilinx ISE support for dual/quad core CPUs?, spartan3wiz
    • Re: Xilinx ISE support for dual/quad core CPUs?, Patrick Dubois
    • Re: Xilinx ISE support for dual/quad core CPUs?, vbetz
  • Re: Xilinx ISE support for dual/quad core CPUs?, Michael Schöberl
    • Re: Xilinx ISE support for dual/quad core CPUs?, Daniel S.
    • Re: Xilinx ISE support for dual/quad core CPUs?, steve.lass
      • Re: Xilinx ISE support for dual/quad core CPUs?, Paul Leventis
• Virtex5 LXT and synthesis.., cshroff
  • Re: Virtex5 LXT and synthesis.., John Adair
    • Re: Virtex5 LXT and synthesis.., cshroff
      • Re: Virtex5 LXT and synthesis.., aholtzma
      • Re: Virtex5 LXT and synthesis.., HT-Lab
• Xilinx Synthesis Attribute usage, Joel
  • Re: Xilinx Synthesis Attribute usage, John_H
    • Re: Xilinx Synthesis Attribute usage, Joel
  • Re: Xilinx Synthesis Attribute usage, Nico Coesel
    • Re: Xilinx Synthesis Attribute usage, Joel
      • Re: Xilinx Synthesis Attribute usage, Nico Coesel
      • Re: Xilinx Synthesis Attribute usage, Daniel S.
• MXE compilation error, dhruvakshad
• XILINX ISE: How to define a Internal clock and use it in OFFSET command?, uvbaz
  • Re: XILINX ISE: How to define a Internal clock and use it in OFFSET command?, JustJohn
• chipscope, skyworld
  • Re: chipscope, Martin Thompson
• init of FPGA's Block-RAMs., lochen
  • Re: init of FPGA's Block-RAMs., Barry Brown
  • Re: init of FPGA's Block-RAMs., John_H
  • Re: init of FPGA's Block-RAMs., Jim Wu
• How to generate sgmii interface?, mynewlifever@xxxxxxxxxxxx
  • Re: How to generate sgmii interface?, davide
• old Quartus project files, Manfred Balik
  • Re: old Quartus project files, Subroto Datta
• Problem with XESS XSA 3S1000!, comp.arch.fpga
• How to use the DDR SDRAM instead of Block RAM?, Ken Soon
  • Re: How to use the DDR SDRAM instead of Block RAM?, Daniel S.
    • Re: How to use the DDR SDRAM instead of Block RAM?, Ken Soon
      • Re: How to use the DDR SDRAM instead of Block RAM?, Daniel S.
      • Re: How to use the DDR SDRAM instead of Block RAM?, Ken Soon
      • Re: How to use the DDR SDRAM instead of Block RAM?, Paul
      • Re: How to use the DDR SDRAM instead of Block RAM?, Daniel S.
      • Re: How to use the DDR SDRAM instead of Block RAM?, Duane Clark
      • Re: How to use the DDR SDRAM instead of Block RAM?, Ken Soon
      • Re: How to use the DDR SDRAM instead of Block RAM?, Taylor Hutt
      • Re: How to use the DDR SDRAM instead of Block RAM?, Ken Soon
• DCM Autoconfiguration??, motty
  • Re: DCM Autoconfiguration??, motty
    • Re: DCM Autoconfiguration??, motty
  • Re: DCM Autoconfiguration??, Erik Widding
    • Re: DCM Autoconfiguration??, motty
• XIlinx 9.2 'partition' mode problem - s/w dies...., johnp
  • Re: XIlinx 9.2 'partition' mode problem - s/w dies...., davide
• ChipScope problem: "Waiting for core to be armed"., Rebecca
  • Re: ChipScope problem: "Waiting for core to be armed"., MM
    • Re: ChipScope problem: "Waiting for core to be armed"., Rebecca
      • Re: ChipScope problem: "Waiting for core to be armed"., MM
      • Re: ChipScope problem: "Waiting for core to be armed"., Rebecca
      • Re: ChipScope problem: "Waiting for core to be armed"., MM
      • Re: ChipScope problem: "Waiting for core to be armed"., Rebecca
      • Re: ChipScope problem: "Waiting for core to be armed"., MM
  • Re: ChipScope problem: "Waiting for core to be armed"., Rob Dimond
  • Re: ChipScope problem: "Waiting for core to be armed"., Rebecca
• Verilog DSP Examples (FFT With 32K-Point Transform Length, FIR, IIR, Discrete Cosine Transform (DCT), Convolution 2D), Jhoberg
• Fpga sdr boards / kits, Alex Gibson
• Xilinx Xplorer misfunction, Frai
  • Re: Xilinx Xplorer misfunction, MM
• doubt in verilog coding, ravipativishnu
  • Re: doubt in verilog coding, KJ
    • Re: doubt in verilog coding, ravipativishnu
      • Re: doubt in verilog coding, Rob Dimond
      • Re: doubt in verilog coding, ravipativishnu
      • Re: doubt in verilog coding, cs_posting
• DDR2: Why do I see two edges of a 125MHz DQS on the IDELAY, rob.dimond@xxxxxxxxx
  • Re: DDR2: Why do I see two edges of a 125MHz DQS on the IDELAY, Rob Dimond
• .bit file to VHDL/verilog source code, lingamaneni . naveen
  • <Possible follow-ups>
  • .bit file to VHDL/verilog source code, lingamaneni . naveen
    • Re: .bit file to VHDL/verilog source code, Mark McDougall
      • Re: .bit file to VHDL/verilog source code, Michael Jřrgensen
      • Re: .bit file to VHDL/verilog source code, jbnote
      • Re: .bit file to VHDL/verilog source code, stephen.craven@xxxxxxxxx
      • Re: .bit file to VHDL/verilog source code, Michael Jřrgensen
      • Re: .bit file to VHDL/verilog source code, jbnote
      • Re: .bit file to VHDL/verilog source code, glen herrmannsfeldt
• Welcome to X-Fest 2007, Peter Alfke
• SEC:U Problem getting rid of bit latch errors, maurizio . gencarelli
  • Re: SEC:U Problem getting rid of bit latch errors, KJ
• SEC:U Problem with bit latch warnings, maurizio . gencarelli
  • <Possible follow-ups>
  • SEC:U Problem with bit latch warnings, maurizio . gencarelli
    • Re: SEC:U Problem with bit latch warnings, John_H
• Does anybody work with Sundance Module (smt338vp30-> Virtex II Pro 30), Pablo
  • Re: Does anybody work with Sundance Module (smt338vp30-> Virtex II Pro 30), Frai
  • Re: Does anybody work with Sundance Module (smt338vp30-> Virtex II Pro 30), Martin Thompson
• Clearing fpga internal memory..., Yrjola
  • Re: Clearing fpga internal memory..., John_H
    • Re: Clearing fpga internal memory..., Sylvain Munaut
      • Re: Clearing fpga internal memory..., John_H
    • Re: Clearing fpga internal memory..., Sylvain Munaut
    • Re: Clearing fpga internal memory..., Peter Alfke
      • Re: Clearing fpga internal memory..., glen herrmannsfeldt
      • Re: Clearing fpga internal memory..., Peter Alfke
      • Re: Clearing fpga internal memory..., glen herrmannsfeldt
      • Re: Clearing fpga internal memory..., Daniel S.
      • Re: Clearing fpga internal memory..., Ray Andraka
      • Re: Clearing fpga internal memory..., Daniel S.
      • Re: Clearing fpga internal memory..., Ray Andraka
• Xilinx Netlist, AdamE
  • Re: Xilinx Netlist, Gabor
  • Re: Xilinx Netlist, Andreas Ehliar
    • Re: Xilinx Netlist, Andreas Ehliar
      • Re: Xilinx Netlist, John McCaskill
      • Re: Xilinx Netlist, Andreas Ehliar
      • Re: Xilinx Netlist, Andreas Ehliar
      • Re: Xilinx Netlist, John McCaskill
      • Re: Xilinx Netlist, Andreas Ehliar
      • Re: Xilinx Netlist, AdamE
      • Re: Xilinx Netlist, Tim
• Xilinx FPGA, OFFSET OUT AFTER, uvbaz
  • Re: Xilinx FPGA, OFFSET OUT AFTER, Gabor
    • Re: Xilinx FPGA, OFFSET OUT AFTER, Frai
  • Re: Xilinx FPGA, OFFSET OUT AFTER, johnp
    • Re: Xilinx FPGA, OFFSET OUT AFTER, uvbaz
      • Re: Xilinx FPGA, OFFSET OUT AFTER, jean-baptiste . nouvel
      • Re: Xilinx FPGA, OFFSET OUT AFTER, johnp
• interface ad9229 with altera stratix II, michael
  • Re: interface ad9229 with altera stratix II, Gabor
• Programming XCF from MicroBlaze over JTAG???, Bob Golenda
  • Re: Programming XCF from MicroBlaze over JTAG???, cs_posting
    • Re: Programming XCF from MicroBlaze over JTAG???, Bob Golenda
      • Re: Programming XCF from MicroBlaze over JTAG???, cs_posting
  • Re: Programming XCF from MicroBlaze over JTAG???, jetmarc
    • Re: Programming XCF from MicroBlaze over JTAG???, Bob Golenda
      • Re: Programming XCF from MicroBlaze over JTAG???, MM
      • Re: Programming XCF from MicroBlaze over JTAG???, Antti
      • Re: Programming XCF from MicroBlaze over JTAG???, Bob Golenda
      • Re: Programming XCF from MicroBlaze over JTAG???, MM
      • Re: Programming XCF from MicroBlaze over JTAG???, Bob Golenda
      • Re: Programming XCF from MicroBlaze over JTAG???, cs_posting
      • Re: Programming XCF from MicroBlaze over JTAG???, Bob Golenda
      • Re: Programming XCF from MicroBlaze over JTAG???, cs_posting
      • Re: Programming XCF from MicroBlaze over JTAG???, MM
      • Re: Programming XCF from MicroBlaze over JTAG???, Bob Golenda
      • Re: Programming XCF from MicroBlaze over JTAG???, zcsizmadia@xxxxxxxxx
      • Re: Programming XCF from MicroBlaze over JTAG???, Bob Golenda
      • Re: Programming XCF from MicroBlaze over JTAG???, zcsizmadia@xxxxxxxxx
      • Re: Programming XCF from MicroBlaze over JTAG???, Bob Golenda
      • Re: Programming XCF from MicroBlaze over JTAG???, jetmarc
      • Message not available
      • Re: Programming XCF from MicroBlaze over JTAG???, MM
      • Re: Programming XCF from MicroBlaze over JTAG???, Bob Golenda
      • Re: Programming XCF from MicroBlaze over JTAG???, cs_posting
      • Re: Programming XCF from MicroBlaze over JTAG???, Petter Gustad
      • Re: Programming XCF from MicroBlaze over JTAG???, dscolson@xxxxxxx
      • Re: Programming XCF from MicroBlaze over JTAG???, zcsizmadia@xxxxxxxxx
      • Re: Programming XCF from MicroBlaze over JTAG???, Bob Golenda
• ANNC: Clock Network Implementation Webcast, bart
• qemu+ghdl or uml+ghdl hardware-software cosimulation?, wzab
  • Re: qemu+ghdl or uml+ghdl hardware-software cosimulation?, HT-Lab
• PCI - Express, Tim
  • Re: PCI - Express, Colin Hankins
    • Re: PCI - Express, Tim
• using system ACE for generic app data storage - file system intelligence required?, Jeff Cunningham
  • Re: using system ACE for generic app data storage - file system intelligence required?, Siva Velusamy
• WTF? - Spartan-3E starter kit with no printed board manual?, Uncle Noah
  • Re: WTF? - Spartan-3E starter kit with no printed board manual?, John_H
    • Re: WTF? - Spartan-3E starter kit with no printed board manual?, Uncle Noah
      • Re: WTF? - Spartan-3E starter kit with no printed board manual?, John_H
      • Re: WTF? - Spartan-3E starter kit with no printed board manual?, Eric Crabill
  • Re: WTF? - Spartan-3E starter kit with no printed board manual?, Jim Granville
    • Re: WTF? - Spartan-3E starter kit with no printed board manual?, Benjamin Todd
  • Re: WTF? - Spartan-3E starter kit with no printed board manual?, Daniel S.
    • Re: WTF? - Spartan-3E starter kit with no printed board manual?, Alex Gibson
• Xilinx SRL's and sync flip flops, motty
  • Re: Xilinx SRL's and sync flip flops, Austin Lesea
• sum of array, VHDL_HELP
  • Re: sum of array, John_H
    • Re: sum of array, VHDL_HELP
      • Re: sum of array, John_H
      • Re: sum of array, VHDL_HELP
      • Re: sum of array, John_H
      • Re: sum of array, VHDL_HELP
    • Re: sum of array, VHDL_HELP
    • Re: sum of array, VHDL_HELP
      • Message not available
      • Re: sum of array, VHDL_HELP
      • Re: sum of array, John_H
      • Re: sum of array, VHDL_HELP
      • Re: sum of array, John_H
      • Re: sum of array, Jonathan Bromley
      • Re: sum of array, VHDL_HELP
• Modelsim-SDF-Vital, Ruzica
• Modelsim - SDF incompatibility, Ruzica
• Can you change the default settings for XST when running platgen?, Rick North
• help !something wrong with Adaptive Filter (vhdl code), kangwei365
  • Re: help !something wrong with Adaptive Filter (vhdl code), Mike Treseler
    • Re: help !something wrong with Adaptive Filter (vhdl code), kangwei365@xxxxxxxxx
• faq, 4balaji
  • Re: faq, Daniel S.
• 3.3V tolerant Virtex-4 JTAG Configuration, Dale
  • Re: 3.3V tolerant Virtex-4 JTAG Configuration, Austin Lesea
    • Re: 3.3V tolerant Virtex-4 JTAG Configuration, Dale
• Heatsink on FPGA?, jean-baptiste . nouvel
  • Re: Heatsink on FPGA?, Ray Andraka
    • Re: Heatsink on FPGA?, Daniel S.
      • Re: Heatsink on FPGA?, jean-baptiste . nouvel
      • Re: Heatsink on FPGA?, Daniel S.
  • Re: Heatsink on FPGA?, John Adair
  • Re: Heatsink on FPGA?, Greg Neff
    • Re: Heatsink on FPGA?, jean-baptiste . nouvel
      • Re: Heatsink on FPGA?, Tim
      • Re: Heatsink on FPGA?, Gabor
• /* synopsys enum state_code */ on XST???, jean-baptiste . nouvel
  • Re: /* synopsys enum state_code */ on XST???, Nicolas Paul Collin Gloster
• PAL, Peter Soegaard
  • Re: PAL, Peter Alfke
• Initialization of arrays in Verilog, Till Wollenberg
  • Re: Initialization of arrays in Verilog, Uwe Bonnes
    • Re: Initialization of arrays in Verilog, Till Wollenberg
      • Re: Initialization of arrays in Verilog, Andreas Ehliar
• ISE synthesis works, XPS does not resolve symbol?, Bhanu Chandra
  • Re: ISE synthesis works, XPS does not resolve symbol?, Bhanu Chandra
• Estimating number of FPGAs needed for an application, rbblasco
  • Re: Estimating number of FPGAs needed for an application, Guenter
  • Re: Estimating number of FPGAs needed for an application, comp.arch.fpga
    • Re: Estimating number of FPGAs needed for an application, glen herrmannsfeldt
  • Re: Estimating number of FPGAs needed for an application, Ray Andraka
  • Re: Estimating number of FPGAs needed for an application, glen herrmannsfeldt
    • Re: Estimating number of FPGAs needed for an application, Paul
• Power PC embeded in Virtex II Pro. Could I erase it with a new bitstream?, Pablo
  • Re: Power PC embeded in Virtex II Pro. Could I erase it with a new bitstream?, Andreas Ehliar
    • Re: Power PC embeded in Virtex II Pro. Could I erase it with a new bitstream?, Pablo
      • Re: Power PC embeded in Virtex II Pro. Could I erase it with a new bitstream?, Andreas Ehliar
      • Re: Power PC embeded in Virtex II Pro. Could I erase it with a new bitstream?, Pablo
• EDK & custom board definitions, Andrew Greensted
  • Re: EDK & custom board definitions, John McCaskill
    • Re: EDK & custom board definitions, Andrew Greensted
• Dual edge detection, ALuPin@xxxxxx
  • Re: Dual edge detection, Gabor
    • Re: Dual edge detection, Peter Alfke
      • Re: Dual edge detection, Mike Treseler
  • Re: Dual edge detection, John_H
    • Re: Dual edge detection, ALuPin@xxxxxx
    • Re: Dual edge detection, ALuPin@xxxxxx
      • Re: Dual edge detection, John_H
      • Re: Dual edge detection, Peter Alfke
      • Re: Dual edge detection, Duane Clark
      • Re: Dual edge detection, John_H
• Need help bringing up PCIe at the physical layer., John C . Randolph
• Comunicate FPGA to Ethernet, Himlam8484
• Re: MPD Files, Amit Kasat
• Xilinx: Case Statements, lingwitt
• Design report does not show BRAM usage, Bhanu Chandra
  • Re: Design report does not show BRAM usage, Uwe Bonnes
    • Re: Design report does not show BRAM usage, Bhanu Chandra
      • Re: Design report does not show BRAM usage, Uwe Bonnes
      • Re: Design report does not show BRAM usage, Bhanu Chandra
      • Re: Design report does not show BRAM usage, Bhanu Chandra
      • Re: Design report does not show BRAM usage, Bhanu Chandra
      • Re: Design report does not show BRAM usage, Uwe Bonnes
      • Re: Design report does not show BRAM usage, John McCaskill
  • Re: Design report does not show BRAM usage, Andy Peters
• Are FPGAs go enough for clock dstribution, Ben Popoola
  • Re: Are FPGAs go enough for clock dstribution, Jim Granville
  • Re: Are FPGAs go enough for clock dstribution, Daniel S.
• ddr sdram controller, dhruvakshad
  • Re: ddr sdram controller, Icky Thwacket
  • Re: ddr sdram controller, Daniel S.
    • Re: ddr sdram controller, PeteS
  • Re: ddr sdram controller, birla . manish
    • Re: ddr sdram controller, dhruvakshad
• Addressing scheme in Block RAM, Venu
  • Re: Addressing scheme in Block RAM, Peter Alfke
  • Re: Addressing scheme in Block RAM, John_H
  • Re: Addressing scheme in Block RAM, Ben Jackson
  • Re: Addressing scheme in Block RAM, Peter Alfke
    • Re: Addressing scheme in Block RAM, Paul
      • Re: Addressing scheme in Block RAM, Venu
      • Re: Addressing scheme in Block RAM, Venu
      • Re: Addressing scheme in Block RAM, Venu
      • Re: Addressing scheme in Block RAM, John_H
      • Re: Addressing scheme in Block RAM, Peter Alfke
      • Re: Addressing scheme in Block RAM, Daniel S.
• Any Western NC VHDL Designers?, Hawker
• XST 9.1 hates VHDL character types, Andy Peters
  • Re: XST 9.1 hates VHDL character types, Andy Peters
• Re: Xilinx Platform cable USB and impact on linux without windrvr, Grant Likely
  • Re: Xilinx Platform cable USB and impact on linux without windrvr, Sylvain Munaut
    • Re: Xilinx Platform cable USB and impact on linux without windrvr, Michael Gernoth
  • Re: Xilinx Platform cable USB and impact on linux without windrvr, Sean Durkin
  • <Possible follow-ups>
  • Re: Xilinx Platform cable USB and impact on linux without windrvr, Luzerne
    • Re: Xilinx Platform cable USB and impact on linux without windrvr, Uwe Bonnes
      • Re: Xilinx Platform cable USB and impact on linux without windrvr, Michael Gernoth
      • Re: Xilinx Platform cable USB and impact on linux without windrvr, Luzerne
  • Re: Xilinx Platform cable USB and impact on linux without windrvr, carlos . asmat
    • Re: Xilinx Platform cable USB and impact on linux without windrvr, Luzerne
      • Re: Xilinx Platform cable USB and impact on linux without windrvr, carlos . asmat
      • Re: Xilinx Platform cable USB and impact on linux without windrvr, Luzerne
    • Re: Xilinx Platform cable USB and impact on linux without windrvr, Michael Gernoth
• Re: Altera PowerPlay Power estimation, mvaria
• Re: How to get ISE to create a _bd.bmm file for BRAM initialization, MM
• Virtex 4 FX12 - where are the EMACs and PPC core located?, Markus Zingg
  • Re: Virtex 4 FX12 - where are the EMACs and PPC core located?, John McCaskill
    • Re: Virtex 4 FX12 - where are the EMACs and PPC core located?, Markus Zingg
      • Re: Virtex 4 FX12 - where are the EMACs and PPC core located?, John McCaskill
      • Re: Virtex 4 FX12 - where are the EMACs and PPC core located?, Markus Zingg
• Xilin X-Fest Lunacy, MK
  • Re: Xilin X-Fest Lunacy, MK
  • Re: Xilin X-Fest Lunacy, Peter Alfke
    • Re: Xilin X-Fest Lunacy, Jim Granville
      • Re: Xilin X-Fest Lunacy, Tim
  • Re: Xilin X-Fest Lunacy, Peter Alfke
    • Re: Xilin X-Fest Lunacy, Peter Alfke
      • Re: Xilin X-Fest Lunacy, comp.arch.fpga
      • Re: Xilin X-Fest Lunacy, Peter Alfke
      • Re: Xilin X-Fest Lunacy, Peter Alfke
      • Re: Xilin X-Fest Lunacy, John C . Randolph
      • Re: Xilin X-Fest Lunacy, Peter Alfke
      • Re: Xilin X-Fest Lunacy, comp.arch.fpga
      • Re: Xilin X-Fest Lunacy, Peter Alfke
      • Re: Xilin X-Fest Lunacy, Peter Alfke
      • Re: Xilin X-Fest Lunacy, Brian Drummond
      • Re: Xilin X-Fest Lunacy, Austin Lesea
      • Re: Xilin X-Fest Lunacy, Philip Freidin
      • Re: Xilin X-Fest Lunacy, comp.arch.fpga
• RLOC not working correctly in ISE 8.2 and 9.1?, Andreas Ehliar
  • Re: RLOC not working correctly in ISE 8.2 and 9.1?, Ray Andraka
    • Re: RLOC not working correctly in ISE 8.2 and 9.1?, Andreas Ehliar
• data2mem crash, Sylvain Munaut
  • Re: data2mem crash, Andreas Ehliar
• Xilinx Spartan DCM jitter spectrum, Nico Coesel
  • Re: Xilinx Spartan DCM jitter spectrum, Austin Lesea
  • Re: Xilinx Spartan DCM jitter spectrum, ray
• Load V4 bitstream encryption key with XSVF, jetmarc
  • Re: Load V4 bitstream encryption key with XSVF, jetmarc
  • Re: Load V4 bitstream encryption key with XSVF (solved), jetmarc
• Driving PLL from general I/O in Altera Cyclone, nfirtaps
  • Re: Driving PLL from general I/O in Altera Cyclone, Will Dean
    • Re: Driving PLL from general I/O in Altera Cyclone, nfirtaps
      • Re: Driving PLL from general I/O in Altera Cyclone, Will Dean
      • Re: Driving PLL from general I/O in Altera Cyclone, nfirtaps
      • Re: Driving PLL from general I/O in Altera Cyclone, Will Dean
      • Re: Driving PLL from general I/O in Altera Cyclone, nfirtaps
  • Re: Driving PLL from general I/O in Altera Cyclone, Rob
    • Re: Driving PLL from general I/O in Altera Cyclone, nfirtaps
      • Re: Driving PLL from general I/O in Altera Cyclone, Rob
• XILINX ISE PAR error: CLK0_BUFG_INST is not placed, lucaroccasalva
• Xilinx CoreGen fifo - ngdbuild error, Markus Fras
  • Re: Xilinx CoreGen fifo - ngdbuild error, Sean Durkin
    • Re: Xilinx CoreGen fifo - ngdbuild error, Markus Fras
      • Re: Xilinx CoreGen fifo - ngdbuild error, Sean Durkin
• CAN vhdl code document, barukula . ramesh
  • Re: CAN vhdl code document, Tom
• odd warning in Xilinx ISE webpack, Steve Battazzo
  • Re: odd warning in Xilinx ISE webpack, davide
    • Re: odd warning in Xilinx ISE webpack, None
    • Re: odd warning in Xilinx ISE webpack, Steve Battazzo
      • Re: odd warning in Xilinx ISE webpack, Paul
  • Re: odd warning in Xilinx ISE webpack, Andy Peters
    • Re: odd warning in Xilinx ISE webpack, Brian Davis
    • Re: odd warning in Xilinx ISE webpack, Martin Thompson
• Avnet Virtex-4 FX12 mini module, jrabbani
  • Re: Avnet Virtex-4 FX12 mini module, Daniel S.
    • Re: Avnet Virtex-4 FX12 mini module, Andreas Ehliar
      • Re: Avnet Virtex-4 FX12 mini module, jrabbani
      • Re: Avnet Virtex-4 FX12 mini module, Andreas Ehliar
      • Re: Avnet Virtex-4 FX12 mini module, davide
• FPGA Vs ASIC design and implementation, Karl
  • Re: FPGA Vs ASIC design and implementation, Thomas Stanka
  • Re: FPGA Vs ASIC design and implementation, comp.arch.fpga
  • Re: FPGA Vs ASIC design and implementation, Daniel S.
    • Re: FPGA Vs ASIC design and implementation, Thomas Stanka
      • Re: FPGA Vs ASIC design and implementation, Daniel S.
• using XIlinx impact in batch mode to generate EEPROM files, dipumisc
  • Re: using XIlinx impact in batch mode to generate EEPROM files, Alan Nishioka
    • Re: using XIlinx impact in batch mode to generate EEPROM files, Brian Drummond
      • Re: using XIlinx impact in batch mode to generate EEPROM files, dipumisc
  • Re: using XIlinx impact in batch mode to generate EEPROM files, Martin Thompson
• Introducing picosecond delay between two output signals, axr0284
  • Re: Introducing picosecond delay between two output signals, Austin Lesea
    • Re: Introducing picosecond delay between two output signals, Ulrich Bangert
      • Re: Introducing picosecond delay between two output signals, Daniel S.
      • Re: Introducing picosecond delay between two output signals, axr0284
      • Re: Introducing picosecond delay between two output signals, John_H
      • Re: Introducing picosecond delay between two output signals, jhmccaskill
      • Re: Introducing picosecond delay between two output signals, Daniel S.
      • Re: Introducing picosecond delay between two output signals, Austin Lesea
  • Re: Introducing picosecond delay between two output signals, John_H
  • Re: Introducing picosecond delay between two output signals, Manny
  • Re: Introducing picosecond delay between two output signals, Peter Alfke
  • Re: Introducing picosecond delay between two output signals, KJ
  • Re: Introducing picosecond delay between two output signals, Brian Drummond
  • Re: Introducing picosecond delay between two output signals, Jerry Coffin
  • Re: Introducing picosecond delay between two output signals, Paul
• DFF with clock and async-preset tied together, Marlboro
  • Re: DFF with clock and async-preset tied together, Mike Treseler
• Spartan3AN - Roadmap, news.t-online.de
  • Re: Spartan3AN - Roadmap, Matthew Hicks
    • Re: Spartan3AN - Roadmap, Paul
      • Re: Spartan3AN - Roadmap, Matthew Hicks
      • Re: Spartan3AN - Roadmap, Jim Granville
  • Re: Spartan3AN - Roadmap, Peter Alfke
    • Re: Spartan3AN - Roadmap, Brian Drummond
  • Re: Spartan3AN - Roadmap, Jim Granville
    • Re: Spartan3AN - Roadmap, John McGrath
      • Re: Spartan3AN - Roadmap, Jim Granville
      • Re: Spartan3AN - Roadmap - bigger questions may prevail..., Austin Lesea
      • Re: Spartan3AN - Roadmap - bigger questions may prevail..., Jim Granville
      • Re: Spartan3AN - Roadmap - bigger questions may prevail..., Austin Lesea
      • Re: Spartan3AN - Roadmap - bigger questions may prevail..., Symon
      • Re: Spartan3AN - Roadmap - bigger questions may prevail..., Austin Lesea
      • Re: Spartan3AN - Roadmap - bigger questions may prevail..., John McCaskill
      • Re: Spartan3AN - Roadmap - bigger questions may prevail..., Symon
      • Re: Spartan3AN - Roadmap - bigger questions may prevail..., John McCaskill
      • Re: Spartan3AN - Roadmap - bigger questions may prevail..., Eric Smith
    • Re: Spartan3AN - Roadmap, Carlhermann Schlehaus
    • Re: Spartan3AN - Roadmap, dalai lamah
  • Re: Spartan3AN - Roadmap, Andy Peters
    • Re: Spartan3AN - Roadmap, Jim Granville
• DCI termination mismatch error reported in ise91, mini_monkey
• Re: VHDL and Latch, Symon
  • Re: VHDL and Latch, Peter Alfke
    • Re: VHDL and Latch, Symon
      • Re: VHDL and Latch, John_H
      • Re: VHDL and Latch, Weng Tianxiang
      • Re: VHDL and Latch, John_H
      • Re: VHDL and Latch, Weng Tianxiang
• Query regarding Project.Plz help very urgent, pra . vlsi
  • Re: Query regarding Project.Plz help very urgent, Symon
    • Re: Query regarding Project.Plz help very urgent, Alan Nishioka
      • Re: Query regarding Project.Plz help very urgent, Austin Lesea
      • Re: Query regarding Project.Plz help very urgent, langwadt
      • Re: Query regarding Project.Plz help very urgent, Austin Lesea
      • Re: Query regarding Project.Plz help very urgent, Manny
    • Re: Query regarding Project.Plz help very urgent, pra . vlsi
      • Re: Query regarding Project.Plz help very urgent, Uwe Bonnes
  • Re: Query regarding Project.Plz help very urgent, Mike Treseler
• Where do I find CMOS image sensors and lenses?, it . stein
  • Re: Where do I find CMOS image sensors and lenses?, Rob
    • Re: Where do I find CMOS image sensors and lenses?, Gabor
  • Message not available
    • Re: Where do I find CMOS image sensors and lenses?, john.orlando@xxxxxxxxx
  • Re: Where do I find CMOS image sensors and lenses?, birla . manish
  • Re: Where do I find CMOS image sensors and lenses?, birla . manish
  • Re: Where do I find CMOS image sensors and lenses?, Mike Harrison
• No Clock in ChipScope Pro Analyzer, Yaseen Zaidi
  • Re: No Clock in ChipScope Pro Analyzer, Zara
    • Re: No Clock in ChipScope Pro Analyzer, Helmut
      • Re: No Clock in ChipScope Pro Analyzer, Yaseen Zaidi
  • Re: No Clock in ChipScope Pro Analyzer, birla . manish
• Routing problem of DCM, Rebecca
  • Re: Routing problem of DCM, WATomb
    • Re: Routing problem of DCM, Rebecca
      • Re: Routing problem of DCM, MM
    • Re: Routing problem of DCM, Rebecca
      • Re: Routing problem of DCM, Rebecca
      • Re: Routing problem of DCM, WATomb
      • Re: Routing problem of DCM, Daniel S.
  • Re: Routing problem of DCM, Rebecca
• ISE & EDK on 64 bits linux machines - install story ;), Sylvain Munaut
• Block RAM in VirtexE FPGA - 'Read-after-Write' and 'No-Read-on-Write' modes, wojt
  • Re: Block RAM in VirtexE FPGA - 'Read-after-Write' and 'No-Read-on-Write' modes, John_H
  • Re: Block RAM in VirtexE FPGA - 'Read-after-Write' and 'No-Read-on-Write' modes, Peter Alfke
  • Re: Block RAM in VirtexE FPGA - 'Read-after-Write' and 'No-Read-on-Write' modes, Weng Tianxiang
    • Re: Block RAM in VirtexE FPGA - 'Read-after-Write' and 'No-Read-on-Write' modes, Peter Alfke
      • Re: Block RAM in VirtexE FPGA - 'Read-after-Write' and 'No-Read-on-Write' modes, Weng Tianxiang
• Xilinx Ise 6.3i, Pablo
  • Re: Xilinx Ise 6.3i, Austin Lesea
• A Very good VLSI Chip design website, chipdesignart
  • Re: A Very good VLSI Chip design website, ram
  • Re: A Very good VLSI Chip design website, Francesco
• Multiple devices within one ISE project, Jean Nicolle
  • Re: Multiple devices within one ISE project, MM
  • Re: Multiple devices within one ISE project, Jim Wu
  • Re: Multiple devices within one ISE project, Andy Peters
    • Re: Multiple devices within one ISE project, Phil Hays
• Xilinx: it's about time!, Andy Peters
• EDK 9.1 when?, MM
  • Re: EDK 9.1 when?, Jon Beniston
    • Re: EDK 9.1 when?, MM
      • Re: EDK 9.1 when?, Jon Beniston
• Ise foundation and Ise Webpack, Pablo
  • Re: Ise foundation and Ise Webpack, steve.lass
• Nios II Multiprocessor Collection run in command line, Ewa
• Re: SCons build tool as an alternative to makefiles, Patrick Dubois
  • Re: SCons build tool as an alternative to makefiles, Martin Thompson
    • Re: SCons build tool as an alternative to makefiles, Patrick Dubois
      • Re: SCons build tool as an alternative to makefiles, Martin Thompson
      • Re: SCons build tool as an alternative to makefiles, Patrick Dubois
      • Re: SCons build tool as an alternative to makefiles, Martin Thompson
• LCD code, meshoshow
  • Re: LCD code, Benjamin Todd
    • Re: LCD code, Pit
• is bluespec pupolar in industry?, CMOS
• Ideas for Masters Project., RaKa
  • Re: Ideas for Masters Project., wallge
  • Re: Ideas for Masters Project., msg
    • Re: Ideas for Masters Project., WATomb
  • Re: Ideas for Masters Project., Jim Granville
  • Re: Ideas for Masters Project., HT-Lab
• Integrate custom cores within Core Generator, El Mehdi Taileb
  • Re: Integrate custom cores within Core Generator, El Mehdi Taileb
• Re: Digital AM/FM Receiver, morpheus
  • Re: Digital AM/FM Receiver, Eric Smith
• Large power planes vs. power islands vs. slits for decoupling, Marc Battyani
  • Re: Large power planes vs. power islands vs. slits for decoupling, Tim
    • Re: Large power planes vs. power islands vs. slits for decoupling, Jim Granville
    • Re: Large power planes vs. power islands vs. slits for decoupling, Symon
      • Re: Large power planes vs. power islands vs. slits for decoupling, Marc Battyani
      • Re: Large power planes vs. power islands vs. slits for decoupling, Symon
  • Re: Large power planes vs. power islands vs. slits for decoupling, Austin
    • Re: Large power planes vs. power islands vs. slits for decoupling, Tim
      • Re: Large power planes vs. power islands vs. slits for decoupling, Austin
    • Re: Large power planes vs. power islands vs. slits for decoupling, Jim Granville
      • Re: Large power planes vs. power islands vs. slits for decoupling, Austin
    • Re: Large power planes vs. power islands vs. slits for decoupling, colin
      • Re: Large power planes vs. power islands vs. slits for decoupling, Austin Lesea
    • Re: Large power planes vs. power islands vs. slits for decoupling, Symon
      • Re: Large power planes vs. power islands vs. slits for decoupling, Jim Granville
      • Re: Large power planes vs. power islands vs. slits for decoupling, Symon
      • Re: Large power planes vs. power islands vs. slits for decoupling, Jim Granville
    • Re: Large power planes vs. power islands vs. slits for decoupling, Symon
    • Re: Large power planes vs. power islands vs. slits for decoupling, Symon
    • Re: Large power planes vs. power islands vs. slits for decoupling, Symon
    • Re: Large power planes vs. power islands vs. slits for decoupling, Symon
      • Re: Large power planes vs. power islands vs. slits for decoupling, sweir
      • Re: Large power planes vs. power islands vs. slits for decoupling, Symon
      • Re: Large power planes vs. power islands vs. slits for decoupling, Tim
      • Re: Large power planes vs. power islands vs. slits for decoupling, Marc Battyani
      • Re: Large power planes vs. power islands vs. slits for decoupling, sweir
      • Re: Large power planes vs. power islands vs. slits for decoupling, Martin Thompson
      • Re: Large power planes vs. power islands vs. slits for decoupling, Marc Battyani
    • Re: Large power planes vs. power islands vs. slits for decoupling, Marc Battyani
      • Re: Large power planes vs. power islands vs. slits for decoupling, Symon
      • Re: Large power planes vs. power islands vs. slits for decoupling, Austin Lesea
      • Re: Large power planes vs. power islands vs. slits for decoupling, glen herrmannsfeldt
      • Re: Large power planes vs. power islands vs. slits for decoupling, KJ
      • Re: Large power planes vs. power islands vs. slits for decoupling, glen herrmannsfeldt
• Call for papers on Hardware Architectures for Genetic, Neural and Fuzzy Systems, nadia@xxxxxxxxxxx
• EDK 8.1i : add port for component, Thang Nguyen
  • Re: EDK 8.1i : add port for component, Thang Nguyen
  • Re: EDK 8.1i : add port for component, Thang Nguyen
  • Re: EDK 8.1i : add port for component, Thang Nguyen
• regarding power and timing, ram
• CUDD, Mr B
  • Re: CUDD, Mr B
• Boot uClinux from RAM without flash, Lancer
  • Re: Boot uClinux from RAM without flash, John Williams
• Re: How to get the area/time results without IO mapping, John McCaskill
• Multiplication operation, VHDL_HELP
  • Re: Multiplication operation, John_H
    • Re: Multiplication operation, John_H
    • Re: Multiplication operation, Matthew Hicks
      • Re: Multiplication operation, VHDL_HELP
      • Re: Multiplication operation, Matthew Hicks
      • Re: Multiplication operation, John_H
      • Re: Multiplication operation, VHDL_HELP
      • Re: Multiplication operation, Matthew Hicks
      • Re: Multiplication operation, John_H
      • Re: Multiplication operation, VHDL_HELP
      • Re: Multiplication operation, VHDL_HELP
      • Re: Multiplication operation, Peter Alfke
      • Re: Multiplication operation, Dave
      • Re: Multiplication operation, John_H
      • Re: Multiplication operation, Peter Alfke
      • Re: Multiplication operation, Matthew Hicks
      • Re: Multiplication operation, Daniel S.
      • Re: Multiplication operation, Paul
• V.34 Modem IP core, GX
  • Re: V.34 Modem IP core, Eric Smith
    • Re: V.34 Modem IP core, GX
      • Re: V.34 Modem IP core, Eric Smith
      • Re: V.34 Modem IP core, GX
      • Re: V.34 Modem IP core, GX
• New modelsim PE student edition 6.2g and Xilinx ISE 9.1i User Linking problems, kaosnannaz
  • Re: New modelsim PE student edition 6.2g and Xilinx ISE 9.1i User Linking problems, Brandon Jasionowski
    • Re: New modelsim PE student edition 6.2g and Xilinx ISE 9.1i User Linking problems, kaosnannaz
      • Re: New modelsim PE student edition 6.2g and Xilinx ISE 9.1i User Linking problems, davide
• DRP of the Virtex 5 PLL, Sylvain Munaut
• Re: Virtex 4 SATA redux, Simon Tam
• Sources (products) for Cannibalizing FPGAs, PLDs, etc., msg
  • Re: Sources (products) for Cannibalizing FPGAs, PLDs, etc., msg
    • Re: Sources (products) for Cannibalizing FPGAs, PLDs, etc., pbFJKD
      • Re: Sources (products) for Cannibalizing FPGAs, PLDs, etc., msg
    • Re: Sources (products) for Cannibalizing FPGAs, PLDs, etc., Ben Jackson
      • Re: Sources (products) for Cannibalizing FPGAs, PLDs, etc., msg
  • Re: Sources (products) for Cannibalizing FPGAs, PLDs, etc., cs_posting
    • Re: Sources (products) for Cannibalizing FPGAs, PLDs, etc., msg
• help read a pixel for picture, VHDL_HELP
  • Re: help read a pixel for picture, Brandon Jasionowski
  • Re: help read a pixel for picture, MM
• Instance Name Being Removed?, Brandon Jasionowski
  • Re: Instance Name Being Removed?, Brandon Jasionowski
    • Re: Instance Name Being Removed?, Sean Durkin
      • Re: Instance Name Being Removed?, Brandon Jasionowski
      • Re: Instance Name Being Removed?, John McCaskill
      • Re: Instance Name Being Removed?, Brandon Jasionowski
• XST ucf timespec, jonas
  • Re: XST ucf timespec, Gabor
• OPB-to-PLB bridge, eascheiber
  • Re: OPB-to-PLB bridge, jetmarc
• Re: Xilinx ISE webpack in Ubuntu?, Steve Battazzo
  • Re: Xilinx ISE webpack in Ubuntu?, Andreas Ehliar
  • Re: Xilinx ISE webpack in Ubuntu?, Luzerne
    • Re: Xilinx ISE webpack in Ubuntu?, Steve Battazzo
  • Re: Xilinx ISE webpack in Ubuntu?, aholtzma
    • Re: Xilinx ISE webpack in Ubuntu?, Steve Battazzo
• How to connect an IP to OPB bus??, Sandip
  • Re: How to connect an IP to OPB bus??, Zara
  • Re: How to connect an IP to OPB bus??, Frank van Eijkelenburg
• Virtex-5 are available from distribution, Peter Alfke
• What is the running frequency for a typical FPGA application using Virtex 5, Weng Tianxiang
  • Re: What is the running frequency for a typical FPGA application using Virtex 5, Ray Andraka
    • Re: What is the running frequency for a typical FPGA application using Virtex 5, Weng Tianxiang
• Help with Partial Reconfiguration on Spartan3, lucaroccasalva
  • Re: Help with Partial Reconfiguration on Spartan3, salorankatu
• apologia, Austin Lesea
  • Re: apologia, Tim
    • Re: apologia, Austin Lesea
• xilinx block ram synthesis, S.T.
  • Re: xilinx block ram synthesis, John_H
    • Re: xilinx block ram synthesis, nagaraj
      • Re: xilinx block ram synthesis, S.T.
      • Re: xilinx block ram synthesis, John_H
      • Re: xilinx block ram synthesis, Daniel S.
      • Re: xilinx block ram synthesis, nagaraj
      • Re: xilinx block ram synthesis, Daniel S.
  • Re: xilinx block ram synthesis, Andy Peters
    • Re: xilinx block ram synthesis, S.T.
      • Re: xilinx block ram synthesis, John_H
      • Re: xilinx block ram synthesis, S.T.
      • Re: xilinx block ram synthesis, Daniel S.
• looking for the source VHDL for Jpeg 2000, Frederic
  • Re: looking for the source VHDL for Jpeg 2000, Sylvain Munaut
    • Re: looking for the source VHDL for Jpeg 2000, Frederic
• Xilinx ISE Webpack 9.1 RTL schematic viewer problem, Robert Ganter
• Bypass caps, X2Y and 'puddles'., Symon
  • Re: Bypass caps, X2Y and 'puddles'., Austin Lesea
  • Re: Bypass caps, X2Y and 'puddles'., Bob Perlman
    • Re: Bypass caps, X2Y and 'puddles'., Symon
  • Re: Bypass caps, X2Y and 'puddles'., Jim Granville
    • Re: Bypass caps, X2Y and 'puddles'., Tim
  • Re: Bypass caps, X2Y and 'puddles'., Marc Battyani
    • Re: Bypass caps, X2Y and 'puddles'., Symon
      • Re: Bypass caps, X2Y and 'puddles'., Marc Battyani
      • Re: Bypass caps, X2Y and 'puddles'., Symon
      • Re: Bypass caps, X2Y and 'puddles'., Marc Battyani
      • Re: Bypass caps, X2Y and 'puddles'., Symon
• Potential problem in batch files for Xilinx [was SCons build tool as an alternative to makefiles], Martin Thompson
  • Re: Potential problem in batch files for Xilinx [was SCons build tool as an alternative to makefiles], Patrick Dubois
    • Re: Potential problem in batch files for Xilinx, Martin Thompson
      • Re: Potential problem in batch files for Xilinx, aholtzma
      • Re: Potential problem in batch files for Xilinx, Martin Thompson
  • Re: Potential problem in batch files for Xilinx [was SCons build tool as an alternative to makefiles], Jim Wu
    • Re: Potential problem in batch files for Xilinx, Martin Thompson
      • Re: Potential problem in batch files for Xilinx, Jim Wu
      • Re: Potential problem in batch files for Xilinx, Martin Thompson
• XPS (NGCBUILD) fails when creates netlist: "failed to copy to implementation", ferorcue
  • Re: XPS (NGCBUILD) fails when creates netlist: "failed to copy to implementation", John McCaskill
• google tech talks : "General Purpose, Low Power Supercomputing Using Reconfiguration", rponsard
• what about dma scatter /gather support in xilinx edk ipif ?, huangjie
• Regional Clock Network and Large Designs, Brandon Jasionowski
  • Re: Regional Clock Network and Large Designs, John McCaskill
    • Re: Regional Clock Network and Large Designs, Brandon Jasionowski
      • Re: Regional Clock Network and Large Designs, Jim Wu
• Where can i get free CAN VHDL core, raju . penum
  • Re: Where can i get free CAN VHDL core, rponsard
  • Re: Where can i get free CAN VHDL core, Tom
    • Re: Where can i get free CAN VHDL core, raju
• Re: Spartan MicroBlaze, John Williams
• Re: How to implement pipeline in this case?, Derek Simmons
  • <Possible follow-ups>
  • Re: How to implement pipeline in this case?, Daniel S.
    • Re: How to implement pipeline in this case?, Mike Treseler
      • Re: How to implement pipeline in this case?, Daniel S.
      • Re: How to implement pipeline in this case?, Mike Treseler
      • Re: How to implement pipeline in this case?, Daniel S.
      • Re: How to implement pipeline in this case?, Attila Kinali
      • Re: How to implement pipeline in this case?, Daniel S.
      • Re: How to implement pipeline in this case?, Patrick Dubois
      • Re: How to implement pipeline in this case?, Tim
      • Re: How to implement pipeline in this case?, Patrick Dubois
      • Re: How to implement pipeline in this case?, Daniel S.
      • Re: How to implement pipeline in this case?, Patrick Dubois
      • Re: How to implement pipeline in this case?, Daniel S.
      • Re: How to implement pipeline in this case?, Attila Kinali
      • Re: How to implement pipeline in this case?, Patrick Dubois
      • Re: How to implement pipeline in this case?, Jim Lewis
• Re: Virtex 4 FX Sonet Alignment, lb . edc
  • Re: Virtex 4 FX Sonet Alignment, comp.arch.fpga
  • <Possible follow-ups>
  • Re: Virtex 4 FX Sonet Alignment, comp.arch.fpga
    • Re: Virtex 4 FX Sonet Alignment, comp.arch.fpga
• Re: XC3S400 and XC3S500E in PQ208, Symon
  • Re: XC3S400 and XC3S500E in PQ208, Tim
    • Re: XC3S400 and XC3S500E in PQ208, Symon
  • <Possible follow-ups>
  • Re: XC3S400 and XC3S500E in PQ208, Josep Duran
  • Re: XC3S400 and XC3S500E in PQ208, Uwe Bonnes
    • Re: XC3S400 and XC3S500E in PQ208, Jim Granville
      • Re: XC3S400 and XC3S500E in PQ208, Uwe Bonnes
• Re: Making a 32KB BRAM block, virtex-4, Daniel S.
  • Re: Making a 32KB BRAM block, virtex-4, Tim
    • Re: Making a 32KB BRAM block, virtex-4, Daniel S.
      • Re: Making a 32KB BRAM block, virtex-4, Peter Alfke
• Re: Spartan-3AN, Ray Andraka
  • <Possible follow-ups>
  • Re: Spartan-3AN, lb . edc
    • Re: Spartan-3AN, Jim Granville
  • Re: Spartan-3AN, Steve Knapp (Xilinx Spartan-3 Generation FPGAs)
  • Re: Spartan-3AN, doug
• Re: PCI-E TS1s, TC
  • Re: PCI-E TS1s, Fred
    • Re: PCI-E TS1s, TC
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• Re: Xilinx USB flatform cable length mistery ?, davide
  • Re: Xilinx USB flatform cable length mistery ?, Austin Lesea

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