comp.arch.fpga

• Date Index

---

• EDA course development, pallav
• virtex4 configuration via XCF32P Prom, matteo
• Question about simple design, carshie
  • Re: Question about simple design, Gabor
    • Re: Question about simple design, carshie
• Re: DDR FPGA Design, Tommy Thorn
  • Re: DDR FPGA Design, Peter Alfke
  • Re: DDR FPGA Design, Nico Coesel
• Where is help for schematic entry?, carshie
  • Re: Where is help for schematic entry?, carshie
  • Re: Where is help for schematic entry?, Duane Clark
• Synthesis of DSP algorithms, Manny
• cpld version?, carshie
  • Re: cpld version?, Uwe Bonnes
    • Re: cpld version?, Benjamin Todd
    • Re: cpld version?, carshie
      • Re: cpld version?, davide
      • Re: cpld version?, carshie
      • Re: cpld version?, John_H
      • Re: cpld version?, carshie
      • Re: cpld version?, Peter Alfke
• Re: How to get ISE to create a _bd.bmm file for BRAM initialization, Steve
• Graphics demo using FPGA?, Dennis Yurichev
  • Re: Graphics demo using FPGA?, Andreas Ehliar
  • Re: Graphics demo using FPGA?, Matthias Alles
• UNKNOWN Processor Version (0) in XMD, Shant
• ahdl --> vhdl, zlotawy
  • Re: ahdl --> vhdl, Mike Treseler
• Help with Xilinx i/o constracint for ps/2 port, fp
  • Re: Help with Xilinx i/o constracint for ps/2 port, Andy Peters
• how does z-transforms (basically the mathematical techniques in designing digital systems) map with FPGA implementations, CMOS
  • Re: how does z-transforms (basically the mathematical techniques in designing digital systems) map with FPGA implementations, Derek
  • Re: how does z-transforms (basically the mathematical techniques in designing digital systems) map with FPGA implementations, glen herrmannsfeldt
• How to use the test bench wave form simulator?, boled
  • Re: How to use the test bench wave form simulator?, Mike Lewis
    • Re: How to use the test bench wave form simulator?, boled
  • Re: How to use the test bench wave form simulator?, Andy Peters
    • Re: How to use the test bench wave form simulator?, boled
      • Re: How to use the test bench wave form simulator?, Duth
• help with Design Compiler -> Quartus, Sebastian Schüppel
  • Re: help with Design Compiler -> Quartus, Ben Twijnstra
• Re: 1 Gbps - state of the art?, Tim
  • <Possible follow-ups>
  • Re: 1 Gbps - state of the art?, Jim Granville
    • Re: 1 Gbps - state of the art?, PeteS
• XUP Virtex-II Pro, Woutervh
• Differential pairs per Bank, Thomas Reinemann
  • Re: Differential pairs per Bank, Sean Durkin
  • Re: Differential pairs per Bank, Uwe Bonnes
    • Re: Differential pairs per Bank, Symon
      • Re: Differential pairs per Bank, Uwe Bonnes
• Initialisation of two dimensional array to known non-zero values in verilog, sudheer
• linuxppc on ML403, Ricky
• Re: How to perform a boundary scan test BEFORE configuration on Spartan-3 Starter Board ?, BODDU Lokesh
  • Re: How to perform a boundary scan test BEFORE configuration on Spartan-3 Starter Board ?, davide
• FPGA : Jobs required, bijoy
• Linux on Virtex 4?, Bill
  • Re: Linux on Virtex 4?, John Williams
  • Re: Linux on Virtex 4?, Bill
  • Re: Linux on Virtex 4?, Nitro
• Change ROM contents, .bit file, Phil
  • Re: Change ROM contents, .bit file, davide
  • Re: Change ROM contents, .bit file, Andreas Ehliar
• Xilinx Timing Constraints and failures, moogyd
  • Re: Xilinx Timing Constraints and failures, Phil Hays
• USB 2.0 Streaming using FPGAs, billu
  • Re: USB 2.0 Streaming using FPGAs, g . bernocchi
    • Re: USB 2.0 Streaming using FPGAs, billu
      • Re: USB 2.0 Streaming using FPGAs, Nitro
      • Re: USB 2.0 Streaming using FPGAs, John Williams
      • Re: USB 2.0 Streaming using FPGAs, Georg Acher
      • Re: USB 2.0 Streaming using FPGAs, billu
      • Re: USB 2.0 Streaming using FPGAs, Will Dean
      • Re: USB 2.0 Streaming using FPGAs, Daniel O'Connor
      • Re: USB 2.0 Streaming using FPGAs, cs_posting
  • Re: USB 2.0 Streaming using FPGAs, Andreas Ehliar
    • Re: USB 2.0 Streaming using FPGAs, Matthew Hicks
  • Re: USB 2.0 Streaming using FPGAs, pbFJKD
    • Re: USB 2.0 Streaming using FPGAs, johnp
      • Re: USB 2.0 Streaming using FPGAs, Tim
      • Re: USB 2.0 Streaming using FPGAs, billu
      • Re: USB 2.0 Streaming using FPGAs, Dn38517
      • Re: USB 2.0 Streaming using FPGAs, Will Dean
• Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2), Uwe Bonnes
  • Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2), Jan Panteltje
    • Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2), Jan Panteltje
      • Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2), Uwe Bonnes
      • Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2), Eric Smith
    • Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2), Uwe Bonnes
• DCM instantiation in XPS7.1i and ISE7.1. Bug or error?, chriskoh
• Global Clocks in Xilinx ISE, idp2
  • Re: Global Clocks in Xilinx ISE, jesse lackey
    • Re: Global Clocks in Xilinx ISE, idp2
  • Re: Global Clocks in Xilinx ISE, Ben Jackson
    • Re: Global Clocks in Xilinx ISE, idp2
      • Re: Global Clocks in Xilinx ISE, Gabor
• question about DCM usage in virtex 5, cathy
  • Re: question about DCM usage in virtex 5, Mike Treseler
    • Re: question about DCM usage in virtex 5, cathy
      • Re: question about DCM usage in virtex 5, Mike Treseler
• Conversion from Xilinx ISE 7 to 8 fails, kron
• bram can't store elf, dan
  • Re: bram can't store elf, Martin Thompson
    • Re: bram can't store elf, dan
      • Re: bram can't store elf, Martin Thompson
• virtex-II DCM phase shift problems, jack lee
• Problem with verilog program, canest
  • Re: Problem with verilog program, motty
    • Re: Problem with verilog program, canest
      • Re: Problem with verilog program, glen herrmannsfeldt
      • Re: Problem with verilog program, motty
    • Re: Problem with verilog program, glen herrmannsfeldt
  • Re: Problem with verilog program, Joseph Samson
• Problem with pin assign using CASE, hgs
  • <Possible follow-ups>
  • Problem with pin assign using CASE, hgs
    • Re: Problem with pin assign using CASE, Joseph Samson
    • Re: Problem with pin assign using CASE, hgs
• How to make an internal signal embedded deep in hierarchy to a gloal output signal, Weng Tianxiang
  • Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal, KJ
    • Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal, Weng Tianxiang
      • Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal, Tim
  • Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal, Andrew Holme
    • Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal, Weng Tianxiang
      • Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal, ALuPin@xxxxxx
      • Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal, Jonathan Bromley
  • Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal, Nico Coesel
• Minimal design for xilinx?, canest
  • Re: Minimal design for xilinx?, Ben Jackson
    • Re: Minimal design for xilinx?, Peter Alfke
      • Re: Minimal design for xilinx?, -jg
    • Re: Minimal design for xilinx?, canest
      • Re: Minimal design for xilinx?, Nico Coesel
      • Re: Minimal design for xilinx?, Peter Alfke
      • Re: Minimal design for xilinx?, Jon Elson
      • Re: Minimal design for xilinx?, Ben Jackson
  • Re: Minimal design for xilinx?, -jg
    • Re: Minimal design for xilinx?, HT-Lab
  • Re: Minimal design for xilinx?, Peter Wallace
  • Re: Minimal design for xilinx?, Leon
  • Re: Minimal design for xilinx?, Ray Andraka
    • Re: Minimal design for xilinx?, canest
      • Re: Minimal design for xilinx?, Ray Andraka
      • Re: Minimal design for xilinx?, glen herrmannsfeldt
  • Re: Minimal design for xilinx?, Benjamin Todd
• Rank order filtering - XAPP953 - what am I doing wrong?, Marek Kraft
• Higher studies, M Ihsan Baig
  • Re: Higher studies, Ben Twijnstra
    • Re: Higher studies, comp.arch.fpga
    • Re: Higher studies, lb . edc
• Anyone have a Lancelot card for sale?, H. Peter Anvin
• Webpack-9.1 working on debian / grml, Jan Panteltje
• Re: Datapath design problem?, JustJohn
• Forcing a LUT to not be optimized, David
  • Re: Forcing a LUT to not be optimized, JustJohn
    • Re: Forcing a LUT to not be optimized, salorankatu
  • Re: Forcing a LUT to not be optimized, Jim Wu
  • Re: Forcing a LUT to not be optimized, John_H
    • Re: Forcing a LUT to not be optimized, David
  • Re: Forcing a LUT to not be optimized, Martin Thompson
• Timing analyzer with Virtex 4, skyworld
  • Re: Timing analyzer with Virtex 4, Symon
    • Re: Timing analyzer with Virtex 4, skyworld
      • Re: Timing analyzer with Virtex 4, Symon
      • Re: Timing analyzer with Virtex 4, skyworld
      • Re: Timing analyzer with Virtex 4, motty
      • Re: Timing analyzer with Virtex 4, skyworld
      • Re: Timing analyzer with Virtex 4, Symon
      • Re: Timing analyzer with Virtex 4, skyworld
• Inferring Xilinx RAM's with Byte enable options, anil
  • Re: Inferring Xilinx RAM's with Byte enable options, Duth
• how do you code this?, aravind
  • Re: how do you code this?, David R Brooks
    • Re: how do you code this?, aravind
      • Re: how do you code this?, David R Brooks
      • Re: how do you code this?, aravind
      • Re: how do you code this?, David R Brooks
  • Re: how do you code this?, Brian Drummond
    • Re: how do you code this?, Marlboro
      • Re: how do you code this?, aravind
      • Re: how do you code this?, Marlboro
• Timing Diagram Tool, any2letters
  • Re: Timing Diagram Tool, Bob Perlman
  • Re: Timing Diagram Tool, Koen Van Renterghem
    • Re: Timing Diagram Tool, Terry Brown
  • Re: Timing Diagram Tool, Patrick Dubois
• ModelSim Leaf Instances, Brad Smallridge
  • Re: ModelSim Leaf Instances, backhus
  • Re: ModelSim Leaf Instances, Duth
• Can't assign pins in Webpack 8.2i schematic design, Chris Carlen
• Porting MontaVista Linux on ML403, sh3.m4y4
  • <Possible follow-ups>
  • Porting MontaVista Linux on ML403, sh3.m4y4
    • Re: Porting MontaVista Linux on ML403, Ben Jackson
      • Re: Porting MontaVista Linux on ML403, sh3.m4y4
• OrCAD symbol for the Xilinx V5LX50 FF676 device, george_granata
  • Re: OrCAD symbol for the Xilinx V5LX50 FF676 device, Symon
    • Re: OrCAD symbol for the Xilinx V5LX50 FF676 device, Jim Wu
  • Re: OrCAD symbol for the Xilinx V5LX50 FF676 device, davide
  • Re: OrCAD symbol for the Xilinx V5LX50 FF676 device, schsym
• Xilinx USB download cable, Markus Fras
  • Re: Xilinx USB download cable, Ed McGettigan
    • Re: Xilinx USB download cable, Markus Fras
      • Re: Xilinx USB download cable, Andy Peters
      • Re: Xilinx USB download cable, pbFJKD
  • Re: Xilinx USB download cable, davide
• xilinx 8.2 xps debug problems, Ludwig Lenz
  • Re: xilinx 8.2 xps debug problems, Brian Drummond
  • Re: xilinx 8.2 xps debug problems, Thomas Feller
• Simulation of DCM with Xilinx 8.2 and Modelsim 6.1, Frai
• EDK-Modelsim XE, olive_dominguez
• Re: video buffering scheme, nonsequential access (no spatial locality), Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
  • <Possible follow-ups>
  • Re: video buffering scheme, nonsequential access (no spatial locality), Gabor
    • Re: video buffering scheme, nonsequential access (no spatial locality), Pete Fraser
  • Re: video buffering scheme, nonsequential access (no spatial locality), jbnote
  • Re: video buffering scheme, nonsequential access (no spatial locality), JustJohn
  • Re: video buffering scheme, nonsequential access (no spatial locality), Gabor
    • Re: video buffering scheme, nonsequential access (no spatial locality), Marlboro
    • Message not available
      • Re: video buffering scheme, nonsequential access (no spatial locality), Tommy Thorn
      • Re: video buffering scheme, nonsequential access (no spatial locality), Tommy Thorn
    • Message not available
      • Re: video buffering scheme, nonsequential access (no spatial locality), Gabor
• Any UK mirror for ISE 8.2i SP2?, lbo_user
  • Re: Any UK mirror for ISE 8.2i SP2?, John Adair
  • Re: Any UK mirror for ISE 8.2i SP2?, Jim Wu
• IP Protection, nagaraj
  • Re: IP Protection, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
• On-chip randomness (V4FX), jetmarc
  • Re: On-chip randomness (V4FX), Symon
  • Re: On-chip randomness (V4FX), Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
  • Re: On-chip randomness (V4FX), Thomas Stanka
    • Re: On-chip randomness (V4FX), David R Brooks
      • Re: On-chip randomness (V4FX), glen herrmannsfeldt
  • Re: On-chip randomness (V4FX), Ray Andraka
  • Re: On-chip randomness (V4FX), Austin Lesea
    • Re: On-chip randomness (V4FX), Symon
  • Re: On-chip randomness (V4FX), Peter Alfke
    • Re: On-chip randomness (V4FX), H. Peter Anvin
      • Re: On-chip randomness (V4FX), Georg Acher
      • Re: On-chip randomness (V4FX), Symon
      • Re: On-chip randomness (V4FX), Georg Acher
      • Re: On-chip randomness (V4FX), jetmarc
      • Re: On-chip randomness (V4FX), Peter Alfke
• CONDITION VARIABLES IN XILKERNEL, Pablo
• virtex II pro development board(xupv2p) : maximum current driving strength from hirose connector, yashu
• General Number Field Sieve in FPGA, Thomas Langċs
  • Re: General Number Field Sieve in FPGA, Thomas Womack
• Aligning data with clock, Bill
  • Re: Aligning data with clock, bgshea
  • Re: Aligning data with clock, Bill
    • Re: Aligning data with clock, Peter Alfke
    • Re: Aligning data with clock, John_H
  • Re: Aligning data with clock, Bill
• ML403 board - VGA schematics - wrong pins, gsosar
  • Re: ML403 board - VGA schematics - wrong pins, Gerhard Hoffmann
  • Re: ML403 board - VGA schematics - wrong pins, Brad Smallridge
    • Re: ML403 board - VGA schematics - wrong pins, gsosar
      • Re: ML403 board - VGA schematics - wrong pins, gsosar
• Does xiling cpld's need a power supply bypass cap?, imity
  • Re: Does xiling cpld's need a power supply bypass cap?, Tim Wescott
    • Re: Does xiling cpld's need a power supply bypass cap?, imity
      • Re: Does xiling cpld's need a power supply bypass cap?, Peter Alfke
      • Re: Does xiling cpld's need a power supply bypass cap?, -jg
      • Re: Does xiling cpld's need a power supply bypass cap?, Jon Elson
  • Re: Does xiling cpld's need a power supply bypass cap?, Ben Jackson
    • Re: Does xiling cpld's need a power supply bypass cap?, bgshea
• FPGA clock gating ? Or how to avoid it in this case ?, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
  • Re: FPGA clock gating ? Or how to avoid it in this case ?, Symon
    • Re: FPGA clock gating ? Or how to avoid it in this case ?, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
  • Re: FPGA clock gating ? Or how to avoid it in this case ?, Ben Jackson
• attn: marnie - extremely substantial tunes - ewtu lap soz - (1/1), raynor
• book recommendation for self study in digital logic design, Guenter
  • Re: book recommendation for self study in digital logic design, Matthew Hicks
    • Re: book recommendation for self study in digital logic design, Guenter
      • Re: book recommendation for self study in digital logic design, Matthew Hicks
• How to make a clock delay?, anesserm
  • Re: How to make a clock delay?, KJ
    • Re: How to make a clock delay?, anesserm
      • Re: How to make a clock delay?, David R Brooks
• Platform Cable USB & Windows 2003 Server, Helmut
  • Re: Platform Cable USB & Windows 2003 Server, Guy_FPGA
    • Re: Platform Cable USB & Windows 2003 Server, Helmut
      • Re: Platform Cable USB & Windows 2003 Server, Helmut
• uClinux on Spartan 3, Lancer
  • Re: uClinux on Spartan 3, John Williams
    • Re: uClinux on Spartan 3, Lancer
      • Re: uClinux on Spartan 3, John Williams
      • Re: uClinux on Spartan 3, Lancer
      • Re: uClinux on Spartan 3, John Williams
      • Re: uClinux on Spartan 3, Lancer
• ethernet MAC and switch, hema
  • Re: ethernet MAC and switch, Guy_FPGA
  • Re: ethernet MAC and switch, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
• Re: Good hardware design code re-use strategies, reference book, Symon
  • Re: Good hardware design code re-use strategies, reference book, Guenter
• ANNC: Serial RapidIO Webcast, bart
• Re: ABEL to VHDL translate, Thomas W.
  • <Possible follow-ups>
  • Re: ABEL to VHDL translate, Thomas Wesenberg
• FPGA damage from bad bitstream, stephen.craven@xxxxxxxxx
  • Re: FPGA damage from bad bitstream, Nico Coesel
  • Re: FPGA damage from bad bitstream, Austin Lesea
    • Re: FPGA damage from bad bitstream, jbnote
      • Re: FPGA damage from bad bitstream, Austin Lesea
      • Re: FPGA damage from bad bitstream, jbnote
      • Re: FPGA damage from bad bitstream, Austin Lesea
  • Re: FPGA damage from bad bitstream, Jon Elson
    • Re: FPGA damage from bad bitstream, Neil Steiner
      • Re: FPGA damage from bad bitstream, Neil Steiner
    • Re: FPGA damage from bad bitstream, Neil Steiner
      • Re: FPGA damage from bad bitstream, Neil Steiner
  • Re: FPGA damage from bad bitstream, comp.arch.fpga
  • Re: FPGA damage from bad bitstream, Ben Jackson
    • Re: FPGA damage from bad bitstream, pbFJKD
      • Re: FPGA damage from bad bitstream, comp.arch.fpga
      • Re: FPGA damage from bad bitstream, Jon Elson
  • Re: FPGA damage from bad bitstream, hema
• Xilinx plb ipif read fifo, Rune Dahl Jorgensen
• Re: FPGA workstation - should I wait for Window Vista?, pbFJKD
  • Re: FPGA workstation - should I wait for Window Vista?, Joseph Samson
  • <Possible follow-ups>
  • Re: FPGA workstation - should I wait for Window Vista?, Eric Smith
• FPGA power supply design, kunil
  • Re: FPGA power supply design, PeteS
    • Re: FPGA power supply design, Symon
      • Re: FPGA power supply design, PeteS
      • Re: FPGA power supply design, Symon
  • Re: FPGA power supply design, Austin Lesea
    • Re: FPGA power supply design, PeteS
      • Re: FPGA power supply design, PeteS
      • Re: FPGA power supply design, kunil
• iMPACT dont shows erase write options with fpga, blisca
  • Re: iMPACT dont shows erase write options with fpga, Sean Durkin
    • R: iMPACT dont shows erase write options with fpga, blisca
      • Re: R: iMPACT dont shows erase write options with fpga, Ben Jackson
      • Re: R: iMPACT dont shows erase write options with fpga, Sean Durkin
      • Re: R: iMPACT dont shows erase write options with fpga, Ben Jackson
• XdmHelpers:662, skyworld
• low speed USB interface for FPGAs, vu_5421
  • Re: low speed USB interface for FPGAs, Jon Beniston
  • Re: low speed USB interface for FPGAs, Antti
• Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP, nagaraj
  • Re: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP, Symon
    • Re: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP, nagaraj
      • Re: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP, Symon
      • Re: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP, nagaraj
  • Re: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP, Duth
• Xilinx ISE 8.2, bgshea
  • Re: Xilinx ISE 8.2, Eric Smith
    • Re: Xilinx ISE 8.2, Martin Thompson
      • Re: Xilinx ISE 8.2, Daniel O'Connor
      • Re: Xilinx ISE 8.2, Martin Thompson
      • Re: Xilinx ISE 8.2, Daniel O'Connor
      • Re: Xilinx ISE 8.2, Martin Thompson
      • Re: Xilinx ISE 8.2, Daniel O'Connor
      • Re: Xilinx ISE 8.2, Eric Smith
      • Re: Xilinx ISE 8.2, Martin Thompson
      • Re: Xilinx ISE 8.2, Eric Smith
      • Re: Xilinx ISE 8.2, Martin Thompson
  • Re: Xilinx ISE 8.2, dscolson@xxxxxxx
  • Re: Xilinx ISE 8.2, Austin Lesea
    • Re: Xilinx ISE 8.2, doug
      • Re: Xilinx ISE 8.2, bgshea
      • Re: Xilinx ISE 8.2, Sean Durkin
      • Re: Xilinx ISE 8.2, Phil Hays
      • Re: Xilinx ISE 8.2, jbnote
      • Re: Xilinx ISE 8.2, bgshea
      • Re: Xilinx ISE 8.2, Michal HUSEJKO
      • Re: Xilinx ISE 8.2, Martin Thompson
      • Re: Xilinx ISE 8.2, Andreas Ehliar
      • Re: Xilinx ISE 8.2, doug
      • Re: Xilinx ISE 8.2, Austin Lesea
      • Re: Xilinx ISE 8.2, steve.lass
      • Re: Xilinx ISE 8.2, doug
      • Re: Xilinx ISE 8.2, steve.lass
      • Re: Xilinx ISE 8.2, Andy Peters
      • Re: Xilinx ISE 8.2, doug
      • Re: Xilinx ISE 8.2, ammonton
      • Re: Xilinx ISE 8.2, Ben Jones
      • Re: Xilinx ISE 8.2, doug
      • Re: Xilinx ISE 8.2, bgshea
      • Re: Xilinx ISE 8.2, Sean Durkin
      • Re: Xilinx ISE 8.2, Martin Thompson
      • Re: Xilinx ISE 8.2, Sean Durkin
      • Re: Xilinx ISE 8.2, ammonton
      • Re: Xilinx ISE 8.2, steve.lass
      • Re: Xilinx ISE 8.2, Sean Durkin
      • Re: Xilinx ISE 8.2, steve.lass
      • Re: Xilinx ISE 8.2, jesse lackey
• Scrambling for Lattice SC, ALuPin@xxxxxx
• Xilinx doing a re-entry in non-volatile FPGA arena!!!, Antti
  • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, jetq88
    • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, Nico Coesel
      • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, Antti
    • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, Antti
      • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, Benjamin Todd
  • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, pbgbbrsh
  • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, Austin Lesea
    • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, Antti
      • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, Austin Lesea
      • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, radarman
      • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, Antti
      • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, Antti
      • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, John Adair
      • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, Antti
      • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, John Adair
  • Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!, -jg
• Clock constraints, skyworld
  • Re: Clock constraints, Gabor
    • Re: Clock constraints, skyworld
• what happened to modular design in ISE9, backhus
  • Re: what happened to modular design in ISE9, Dolphin
  • Re: what happened to modular design in ISE9, Tim Verstraete
    • Re: what happened to modular design in ISE9, backhus
      • Re: what happened to modular design in ISE9, Duth
• "Divide" a video line in two stripe, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
  • Re: "Divide" a video line in two stripe, jbnote
    • Re: "Divide" a video line in two stripe, jbnote
    • Re: "Divide" a video line in two stripe, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
      • Re: "Divide" a video line in two stripe, jbnote
      • Re: "Divide" a video line in two stripe, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
  • Re: "Divide" a video line in two stripe, Rob
    • Re: "Divide" a video line in two stripe, Peter Alfke
    • Re: "Divide" a video line in two stripe, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
      • Re: "Divide" a video line in two stripe, Rob
  • Re: "Divide" a video line in two stripe, JustJohn
    • Re: "Divide" a video line in two stripe, JustJohn
      • Re: "Divide" a video line in two stripe, jbnote
    • Re: "Divide" a video line in two stripe, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
• Using demo IP libraries?, zwsdotcom
• How to exclude timing violations in Xilinx *.ucf file, Weng Tianxiang
• how to use register to save data, ZHI
  • Re: how to use register to save data, ZHI
  • Re: how to use register to save data, ZHI
  • Re: how to use register to save data, ZHI
  • Re: how to use register to save data, backhus
    • Re: how to use register to save data, ZHI
      • Re: how to use register to save data, backhus
• When do I need reset and clear?, shitsu
• system generator from Xilinx, nbg2006
  • Re: system generator from Xilinx, MM
    • Re: system generator from Xilinx, Ben Jones
      • Re: system generator from Xilinx, MM
      • Re: system generator from Xilinx, Ben Jones
    • Re: system generator from Xilinx, Martin Thompson
• project help, project help
  • Re: project help, Peter Alfke
  • Re: project help, Josep Duran
  • Re: project help, Dave
• digilent nexys vga glitches, Corer
  • Re: digilent nexys vga glitches, Sylvain Munaut
    • Re: digilent nexys vga glitches, Corer
  • Re: digilent nexys vga glitches, Sylvain Munaut
  • Re: digilent nexys vga glitches, Ben Jackson
    • Re: digilent nexys vga glitches, Corer
  • Re: digilent nexys vga glitches, RedskullDC
    • Re: digilent nexys vga glitches, Corer
      • Re: digilent nexys vga glitches, RedskullDC
      • Re: digilent nexys vga glitches, Corer
• suggest me the right fpga, project help
  • Re: suggest me the right fpga, Rob
  • Re: suggest me the right fpga, Peter Alfke
  • Re: suggest me the right fpga, Austin
  • Re: suggest me the right fpga, pbgibbrish
• Correction for hwicap_v1_00_a code, Neil Steiner
  • Re: Correction for hwicap_v1_00_a code, John Williams
    • Re: Correction for hwicap_v1_00_a code, Neil Steiner
• How can I make xst to infer BlockRAM instead of Distributed RAM, geschma
  • Re: How can I make xst to infer BlockRAM instead of Distributed RAM, Andrew Holme
    • Re: How can I make xst to infer BlockRAM instead of Distributed RAM, Andrew Holme
      • Re: How can I make xst to infer BlockRAM instead of Distributed RAM, stephen.craven@xxxxxxxxx
      • Re: How can I make xst to infer BlockRAM instead of Distributed RAM, Ben Jackson
      • Re: How can I make xst to infer BlockRAM instead of Distributed RAM, Duth
  • Re: How can I make xst to infer BlockRAM instead of Distributed RAM, Matthew Hicks
• Final call for papers: Multi-conference, sr
• Altera EP2S60 rebooting itself, Dennis Yurichev
  • Re: Altera EP2S60 rebooting itself, Gabor
    • Re: Altera EP2S60 rebooting itself, jai.dhar@xxxxxxxxx
• SPARC V7 CORE, bm
  • Re: SPARC V7 CORE, Hans
    • Re: SPARC V7 CORE, Uncle Noah
      • Re: SPARC V7 CORE, bm
      • Re: SPARC V7 CORE, Eric Smith
• NetBSD on Xilinx fpga (ported to ML403), pbdelete
• Series DCM's and total Lock Time, moogyd
  • Re: Series DCM's and total Lock Time, motty
    • Re: Series DCM's and total Lock Time, moogyd
  • Re: Series DCM's and total Lock Time, Symon
• Phasse Detector, axalay
  • Re: Phasse Detector, motty
    • Re: Phasse Detector, Tim
  • Re: Phasse Detector, -jg
  • Re: Phasse Detector, PeteS
    • Re: Phasse Detector, Peter Alfke
      • Re: Phasse Detector, PeteS
      • Re: Phasse Detector, axalay
      • Re: Phasse Detector, JustJohn
      • Re: Phasse Detector, -jg
      • Re: Phasse Detector, David R Brooks
      • Re: frequency-Phase Detector?, Austin
      • Re: frequency-Phase Detector?, axalay
      • Re: Phasse Detector, Symon
• FPGA implementation of UHF transmitter in airborne applications, sindhu
  • Re: FPGA implementation of UHF transmitter in airborne applications, Ray Andraka
    • Re: FPGA implementation of UHF transmitter in airborne applications, PeteS
• Timing Delay Definitions, motty
  • Re: Timing Delay Definitions, Symon
    • Re: Timing Delay Definitions, motty
• "Gate" = ???, Austin Lesea
  • Re: "Gate" = ???, John_H
    • Re: "Gate" = ???, Andreas Ehliar
  • Re: "Gate" = ???, mk
  • Re: "Gate" = ???, glen herrmannsfeldt
  • Re: "Gate" = ???, backhus
  • Re: "Gate" = ???, Ray Andraka
    • Re: "Gate" = ???, Austin Lesea
• Beginner VHDL questions, James Wu
  • Re: Beginner VHDL questions, Martin Thompson
  • Re: Beginner VHDL questions, Brian Drummond
  • Re: Beginner VHDL questions, jmoui
  • Re: Beginner VHDL questions, Ben Jones
  • Re: Beginner VHDL questions, Andy
  • Re: Beginner VHDL questions, James
• ISE Simulator Error 222: SuSE 10.1 Linux, Antonio Di Bacco
  • Re: ISE Simulator Error 222: SuSE 10.1 Linux, El-Mehdi Taileb
    • Re: ISE Simulator Error 222: SuSE 10.1 Linux, Antonio Di Bacco
  • Re: ISE Simulator Error 222: SuSE 10.1 Linux, Daniel O'Connor
• TESTAPP_PERIPHERAL FAILED IN ETHERNET, Pablo
• Source Synchronous LVDS Design - Phase Shift in the Timing Analysis?, Christian Wiesner
  • Re: Source Synchronous LVDS Design - Phase Shift in the Timing Analysis?, Christian Wiesner
• Xilinx website login problems, Antti
  • Re: Xilinx website login problems, Christian Wiesner
  • Re: Xilinx website login problems, Zara
    • Re: Xilinx website login problems, Symon
      • Re: Xilinx website login problems, John Adair
      • Re: Xilinx website login problems, Antti
  • Re: Xilinx website login problems, El-Mehdi Taileb
  • Re: Xilinx website login problems, Thomas Feller
• Re: Generation of Divided-by-3 clock, Peter Alfke
  • Re: Generation of Divided-by-3 clock, sudheer
    • Re: Generation of Divided-by-3 clock, Antti
      • Re: Generation of Divided-by-3 clock, topweaver
  • <Possible follow-ups>
  • Re: Generation of Divided-by-3 clock, Symon
  • Re: Generation of Divided-by-3 clock, Peter Alfke
    • Re: Generation of Divided-by-3 clock, sudheer
• ARM AHBA 1Kbyte boundary issue, kelvins
  • Re: ARM AHBA 1Kbyte boundary issue, Jon Beniston
  • Re: ARM AHBA 1Kbyte boundary issue, Charles, NG
    • Re: ARM AHBA 1Kbyte boundary issue, Joseph
    • Re: ARM AHBA 1Kbyte boundary issue, Joseph
• Behavior of REV input in Virtex2 flops?, Neil Steiner
  • Re: Behavior of REV input in Virtex2 flops?, Ed McGettigan
• Process on both edges, John
  • Re: Process on both edges, Ralf Hildebrandt
  • Re: Process on both edges, Brad Smallridge
  • Re: Process on both edges, Matthew Hicks
  • Re: Process on both edges, Erik Widding
• Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology, anand
  • Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology, Brad Smallridge
    • Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology, anand
      • Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology, glen herrmannsfeldt
      • Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology, anand
      • Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology, Will Dean
      • Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology, pbgbbrsh
  • Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology, chris . hallahan
• PCI Card with FPGA, sheikh . m . farhan
  • Re: PCI Card with FPGA, cpope
    • Re: PCI Card with FPGA, sheikh . m . farhan
      • Re: PCI Card with FPGA, cpope
  • Re: PCI Card with FPGA, Symon
  • Re: PCI Card with FPGA, John Adair
  • Re: PCI Card with FPGA, Quesito
  • Re: PCI Card with FPGA, Quesito
    • Re: PCI Card with FPGA, mike_la_jolla
      • Re: PCI Card with FPGA, Symon
      • Re: PCI Card with FPGA, davide
• Ethernet Interface, Surya
  • Re: Ethernet Interface, Uwe Bonnes
  • Re: Ethernet Interface, davide
    • Re: Ethernet Interface, Surya
      • Re: Ethernet Interface, davide
  • Re: Ethernet Interface, kayrock66
• Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use, Al
  • Re: Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use, Al
    • Re: Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use, Al
      • Re: Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use, Jon Beniston
      • Re: Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use, Al
• running applications from external memory, rbal
  • Re: running applications from external memory, Jhlw
    • Re: running applications from external memory, Jhlw
      • Re: running applications from external memory, Jeff Cunningham
      • Re: running applications from external memory, Jhlw
      • Re: running applications from external memory, Jhlw
      • Re: running applications from external memory, Jhlw
    • Re: running applications from external memory, rbal
• Re: PowerPC_DDR_controller, Peter Monta
• Clock Frequency, psgandhi
  • Re: Clock Frequency, Andrew FPGA
    • Re: Clock Frequency, axalay
• interesting article FPGA routing field programmable nanowire interconnect (FPNI), yttrium
  • Re: interesting article FPGA routing field programmable nanowire interconnect (FPNI), Austin Lesea
    • Re: interesting article FPGA routing field programmable nanowire interconnect (FPNI), Ray Andraka
      • Re: interesting article FPGA routing field programmable nanowire interconnect (FPNI), -jg
• microcode in verilog?, Jalen.Ong@xxxxxxxxx
  • Re: microcode in verilog?, Mike Treseler
    • Re: microcode in verilog?, Derek Simmons
    • Re: microcode in verilog?, -jg
  • Re: microcode in verilog?, Andrew Holme
  • Re: microcode in verilog?, PeteS
• Synchronizing four phase-offset clock domains, john . windish
• Setup time path on V4 SX w/ IDELAY, Brandon Jasionowski
  • Re: Setup time path on V4 SX w/ IDELAY, Sean Durkin
• small, free simple state machine processor suggestions?, jonas
  • Re: small, free simple state machine processor suggestions?, Sean Durkin
    • Re: small, free simple state machine processor suggestions?, jonas
  • Re: small, free simple state machine processor suggestions?, Herbert Kleebauer
  • Re: small, free simple state machine processor suggestions?, jonas
  • Re: small, free simple state machine processor suggestions?, Antti
• about XAPP028, axalay
• Two newbie Chipscope questions, kron
  • Re: Two newbie Chipscope questions, Ben Jones
• four phase clock using DCM with xilinx FPGA, skyworld
  • Re: four phase clock using DCM with xilinx FPGA, motty
    • Re: four phase clock using DCM with xilinx FPGA, skyworld
      • Re: four phase clock using DCM with xilinx FPGA, motty
      • Re: four phase clock using DCM with xilinx FPGA, skyworld
      • Re: four phase clock using DCM with xilinx FPGA, motty
      • Re: four phase clock using DCM with xilinx FPGA, skyworld
• Digital Filter and external PLL (VCO), axalay
  • Re: Digital Filter and external PLL (VCO), ray
    • Re: Digital Filter and external PLL (VCO), axalay
  • Re: Digital Filter and external PLL (VCO), Peter Alfke
    • Re: Digital Filter and external PLL (VCO), axalay
• Constraining Multiple clock design, madair
  • Re: Constraining Multiple clock design, Hans
• Verifying a Bidirectional Data Bus, pete o.
• EDIF format, quad
  • <Possible follow-ups>
  • EDIF format, quad
    • Re: EDIF format, Petter Gustad
  • edif format, quad
    • Re: edif format, Neil Steiner
      • Re: edif format, quad
      • Re: edif format, Petter Gustad
      • Re: edif format, Ed McGettigan
      • Re: edif format, Mike Treseler
      • Re: edif format, Petter Gustad
• benchmarks for vhdl, dhruvakshad
• ISE 9.1i and partial reconfiguration, El-Mehdi Taileb
  • Re: ISE 9.1i and partial reconfiguration, Andy Peters
    • Re: ISE 9.1i and partial reconfiguration, -jg
  • Re: ISE 9.1i and partial reconfiguration, Julian Kain
    • Re: ISE 9.1i and partial reconfiguration, El-Mehdi Taileb
• How to ensure Select signal arrives after Input signals changed, Frai
  • Re: How to ensure Select signal arrives after Input signals changed, Frai
  • Re: How to ensure Select signal arrives after Input signals changed, Mike Treseler
• How to install xilinx ise8.2 in Madriva linux, subint
  • Re: How to install xilinx ise8.2 in Madriva linux, Symon
• Gigabit Ethernet UDP/IP, Klaus Falser
  • Re: Gigabit Ethernet UDP/IP, Ben Jackson
    • Re: Gigabit Ethernet UDP/IP, Klaus Falser
  • Re: Gigabit Ethernet UDP/IP, Sylvain Munaut <SomeOne@xxxxxxxxxxxxxx>
  • Re: Gigabit Ethernet UDP/IP, Pablo
  • Re: Gigabit Ethernet UDP/IP, John McCaskill
• SDK 8.2 error 127, Jason
  • Re: SDK 8.2 error 127, Zara
    • Re: SDK 8.2 error 127, Jon Beniston
• Re: Judge complex degree by state numbers?, topweaver
  • Re: Judge complex degree by state numbers?, KJ
    • Re: Judge complex degree by state numbers?, topweaver
• IDELAY and whether pigs can fly..., motty
  • Re: IDELAY and whether pigs can fly..., Mike Treseler
    • Re: IDELAY and whether pigs can fly..., motty
  • Re: IDELAY and whether pigs can fly..., Peter Alfke
    • Re: IDELAY and whether pigs can fly..., motty
• Will FPGAs suit my need?, NickHolby
  • Re: Will FPGAs suit my need?, Icky Thwacket
  • Re: Will FPGAs suit my need?, Austin
  • Re: Will FPGAs suit my need?, John Larkin
  • Re: Will FPGAs suit my need?, Ben Jackson
    • Re: Will FPGAs suit my need?, Nico Coesel
      • Re: Will FPGAs suit my need?, NickHolby
      • Re: Will FPGAs suit my need?, Icky Thwacket
      • Re: Will FPGAs suit my need?, Jonathan Bromley
      • Re: Will FPGAs suit my need?, Icky Thwacket
      • Re: Will FPGAs suit my need?, Symon
      • Re: Will FPGAs suit my need?, Nico Coesel
  • Re: Will FPGAs suit my need?, -jg
  • Re: Will FPGAs suit my need?, NickHolby
  • Re: Will FPGAs suit my need?, samiam
• How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim, Weng Tianxiang
  • Re: How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim, Mike Treseler
    • Re: How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim, Weng Tianxiang
  • Message not available
    • Re: How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim, Weng Tianxiang
• XST bug inferring dynamic shift register, Eric Brombaugh
• FIFO LogiCore with ISE 8.2 ??, Matthieu Cattin
• Stratix RAM limitations, Peter Y
  • Re: Stratix RAM limitations, Hans
    • Re: Stratix RAM limitations, Peter Y
  • Re: Stratix RAM limitations, Rob
• Too many warnings in Modelsim?, Frai
  • Re: Too many warnings in Modelsim?, tgschwind
    • Re: Too many warnings in Modelsim?, Frai
• xc3sprog, Andrew Rogers
  • Re: xc3sprog, Andrew Rogers
    • Re: xc3sprog, Eli Hughes
  • Re: xc3sprog, mmihai
    • Re: xc3sprog, Andrew Rogers
      • Re: xc3sprog, mmihai
  • Re: xc3sprog, John Larkin
• XMD with Microblaze and EDK 8.2, Zara
• Re: ethernet checksum nightmare, glen herrmannsfeldt
  • Re: ethernet checksum nightmare, Mike Treseler
  • <Possible follow-ups>
  • Re: ethernet checksum nightmare, glen herrmannsfeldt
    • Re: ethernet checksum nightmare, Kim Enkovaara
      • Re: ethernet checksum nightmare, glen herrmannsfeldt
• 16-bit DDR memory controller in EDK, sheikh . m . farhan
  • Re: 16-bit DDR memory controller in EDK, cpope
    • Re: 16-bit DDR memory controller in EDK, sheikh . m . farhan
      • Re: 16-bit DDR memory controller in EDK, cpope
  • Re: 16-bit DDR memory controller in EDK, Guru
    • Re: 16-bit DDR memory controller in EDK, sheikh . m . farhan
• user constraint file of slice based bus macro in virtex 4, Perry
• arbitrator, maxascent
  • Re: arbitrator, Derek Simmons
• Xilinx Floorplanner 'Replace All With Placement' and still logic left over!, Craig Yarbrough
  • Re: Xilinx Floorplanner 'Replace All With Placement' and still logic left over!, Brian Drummond
• RocketIO, MGT documentation. Does MGT clcok have to be 50% duty cycle?, Dale
  • Re: RocketIO, MGT documentation. Does MGT clcok have to be 50% duty cycle?, Ed McGettigan
  • Re: RocketIO, MGT documentation. Does MGT clcok have to be 50% duty cycle?, MM
• Xilinx Synchronous FIFOs, Brad Smallridge
  • Re: Xilinx Synchronous FIFOs, Andrew Holme
• picoblaze RS-232 using 62.5 MHz, axr0284
  • Re: picoblaze RS-232 using 62.5 MHz, John_H
    • Re: picoblaze RS-232 using 62.5 MHz, axr0284
      • Re: picoblaze RS-232 using 62.5 MHz, axr0284
      • Re: picoblaze RS-232 using 62.5 MHz, -jg
      • Re: picoblaze RS-232 using 62.5 MHz, Eric Crabill
• Quick question on Coolrunner II IO voltages, PeteS
  • Re: Quick question on Coolrunner II IO voltages, -jg
• EDIF generation from C, quad
  • Re: EDIF generation from C, Amit
  • Re: EDIF generation from C, acd
    • Re: EDIF generation from C, quad
  • Re: EDIF generation from C, Petter Gustad
• altera MAX II dev kit LCD mountings??, jacko
• Santa Clara Connector and LVTTL etc, jacko
• Transport Delays in Modelsim, Kevin Neilson
  • Re: Transport Delays in Modelsim, Jonathan Bromley
    • Re: Transport Delays in Modelsim, Kevin Neilson
      • Re: Transport Delays in Modelsim, Jonathan Bromley
      • Re: Transport Delays in Modelsim, Kevin Neilson
      • Re: Transport Delays in Modelsim, Jonathan Bromley
      • Re: Transport Delays in Modelsim, Brian Drummond
• Can I use 3.3V clock into the MGTCLK? MGT RocketIO, Dale
  • Re: Can I use 3.3V clock into the MGTCLK? MGT RocketIO, Austin Lesea
    • Re: Can I use 3.3V clock into the MGTCLK? MGT RocketIO, Kolja Sulimma
      • Re: Can I use 3.3V clock into the MGTCLK? MGT RocketIO, Austin Lesea
      • Re: Can I use 3.3V clock into the MGTCLK? MGT RocketIO, glen herrmannsfeldt
• LWIP EXAMPLE??, Pablo
  • Re: LWIP EXAMPLE??, Jon Beniston
    • Re: LWIP EXAMPLE??, Pablo
      • Re: LWIP EXAMPLE??, David R Brooks
• Is this Multi-Cycle Path ?, Ved
  • Re: Is this Multi-Cycle Path ?, Gabor
• VHDL Model of a stepper motor, fpgauser
  • Re: VHDL Model of a stepper motor, Jonathan Bromley
  • Re: VHDL Model of a stepper motor, backhus
    • Re: VHDL Model of a stepper motor, fpgauser
• P160 analog module ?, Matthieu Cattin
  • Re: P160 analog module ?, Rob
• crossing clock domain ??, Matthieu Cattin
  • Re: crossing clock domain ??, John_H
    • Re: crossing clock domain ??, Matthieu Cattin
      • Re: crossing clock domain ??, Peter Alfke
      • Re: crossing clock domain ??, Matthew Hicks
      • Re: crossing clock domain ??, John_H
      • Re: crossing clock domain ??, Peter Alfke
      • Re: crossing clock domain ??, Rob
      • Re: crossing clock domain ??, Peter Alfke
      • Re: crossing clock domain ??, Matthew Hicks
      • Re: crossing clock domain ??, Craig Yarbrough
• Operate Flash S29GL-N from Spansion, zhongqiang . cheng
• ise8.1 and 8.2 difference for SIM_CLKIN_CYCLE_JITTER parameter, rajendra
• Is the FSL a good approach for this...?, motty
  • Re: Is the FSL a good approach for this...?, Göran Bilski
• Re: Virtex-II Pro: Reading/Writing data with Compact Flash, abright52
• Delaying signal, John
  • Re: Delaying signal, John
  • Re: Delaying signal, Thomas Stanka
• Possibility of 80188 VHDL core, Tom Lucas
  • Re: Possibility of 80188 VHDL core, Roberto Waltman
    • Re: Possibility of 80188 VHDL core, Tom Lucas
      • Re: Possibility of 80188 VHDL core, Roberto Waltman
• V4FX PPC data cache behaviour?, jetmarc
• crash of xilinx fpga_editor, Perry
• Accessing SATA hard disk for read/write IO through FPGA in an embedded environment, sheikh . m . farhan
  • Re: Accessing SATA hard disk for read/write IO through FPGA in an embedded environment, Mark McDougall
• Quartus II 6.1 Remove Duplicate Logic option removed, Wilhelm . Klink
• Variable clock using Virtex 4?, John
  • Re: Variable clock using Virtex 4?, Austin Lesea
  • Re: Variable clock using Virtex 4?, Peter Alfke
• Re: what are your current SoC design for ?, Peter Y
• Generate ACE File: *.elf does not contain start address, Peter Kampmann
  • Re: Generate ACE File: *.elf does not contain start address, Peter Kampmann
• CREATE FPGA-PC CONNECTION (LWIP, XILNET), Pablo
• Re: Ones' complement addition, glen herrmannsfeldt
  • Re: Ones' complement addition, Phil Hays
    • Re: Ones' complement addition, glen herrmannsfeldt
      • Re: Ones' complement addition, Phil Hays
    • Re: Ones' complement addition, Eric Smith
      • Re: Ones' complement addition, Phil Hays
      • Re: Ones' complement addition, Eric Smith
      • Re: Ones' complement addition, Phil Hays
      • Re: Ones' complement addition, Eric Smith
      • Re: Ones' complement addition, Koen Van Renterghem
      • Re: Ones' complement addition, Koen Van Renterghem
• Re: (-1)*xn operation in FPGA, Bob Perlman
  • <Possible follow-ups>
  • Re: (-1)*xn operation in FPGA, Thomas Stanka
  • Re: (-1)*xn operation in FPGA, KJ
• Build an FPGA programmer cable, Timo Schneider
  • Re: Build an FPGA programmer cable, Pablo
  • Re: Build an FPGA programmer cable, Guenter
    • Re: Build an FPGA programmer cable, Timo Schneider
      • Re: Build an FPGA programmer cable, Antti
  • Message not available
    • Re: Build an FPGA programmer cable, Timo Schneider
• First Picture of Craignell Modules, John Adair
  • Re: First Picture of Craignell Modules, -jg
    • Message not available
      • Re: First Picture of Craignell Modules, -jg
      • Re: First Picture of Craignell Modules, John Adair
      • Re: First Picture of Craignell Modules, Jonathan Bromley
      • Re: First Picture of Craignell Modules, John Adair
  • Re: First Picture of Craignell Modules, pbgbbrsh
    • Re: First Picture of Craignell Modules, Antti
      • Re: First Picture of Craignell Modules, pbFJKD
• how do we connect internals signals(not ports) of submodules in the top level design to trigger ports of the ila core?, CMOS
  • Re: how do we connect internals signals(not ports) of submodules in the top level design to trigger ports of the ila core?, kayrock66
  • Re: how do we connect internals signals(not ports) of submodules in the top level design to trigger ports of the ila core?, Symon
• Re: Is there a simple complex magnitude algorithm in FPGA implementation?, Peppermint Pumpkin
  • Re: Is there a simple complex magnitude algorithm in FPGA implementation?, SunLei
  • <Possible follow-ups>
  • Re: Is there a simple complex magnitude algorithm in FPGA implementation?, Jonathan Bromley
  • Re: Is there a simple complex magnitude algorithm in FPGA implementation?, cpope
  • Re: Is there a simple complex magnitude algorithm in FPGA implementation?, Ray Andraka
  • Re: Is there a simple complex magnitude algorithm in FPGA implementation?, kayrock66
  • Re: Is there a simple complex magnitude algorithm in FPGA implementation?, Bob Perlman
    • Re: Is there a simple complex magnitude algorithm in FPGA implementation?, Ray Andraka
• Does Modelsim XE support coreconnect BFM simulation?, Jeff Cunningham
  • Re: Does Modelsim XE support coreconnect BFM simulation?, John McCaskill
    • Re: Does Modelsim XE support coreconnect BFM simulation?, Jeff Cunningham
• email protection in the list, fpgauser
  • Re: email protection in the list, Sean Durkin
  • Re: email protection in the list, Mike Treseler
    • Re: email protection in the list, fpgauser
• Problem with unused pin on Spartan 2E, Mounard Le Fougueux
  • Re: Problem with unused pin on Spartan 2E, Mike Treseler
  • Re: Problem with unused pin on Spartan 2E, KJ
  • Re: Problem with unused pin on Spartan 2E, Mounard Le Fougueux
    • Re: Problem with unused pin on Spartan 2E, Mike Treseler
  • Re: Problem with unused pin on Spartan 2E, -jg
  • Re: Problem with unused pin on Spartan 2E, kayrock66
    • Re: Problem with unused pin on Spartan 2E, Mounard Le Fougueux
      • Re: Problem with unused pin on Spartan 2E, John_H
• query, premrajan
  • Re: query, Mike Treseler
• data transfer from fast APB clock domain., marco
  • Re: data transfer from fast APB clock domain., Jon Beniston
    • Re: data transfer from fast APB clock domain., marco
  • Re: data transfer from fast APB clock domain., kayrock66
• Help Implementing an 1000Base-T Ethernet on Stratix II GX, jjlindula@xxxxxxxxxxx
  • Re: Help Implementing an 1000Base-T Ethernet on Stratix II GX, Ben Twijnstra
• Xilinx 2-D DCT core (Where?)., Pete Fraser
• Problems with 7:1 LVDS Tx using OSEDES (Xilinx), rao
  • Re: Problems with 7:1 LVDS Tx using OSEDES (Xilinx), Brad Smallridge
    • Re: Problems with 7:1 LVDS Tx using OSEDES (Xilinx), rao
  • Re: Problems with 7:1 LVDS Tx using OSEDES (Xilinx), yttrium
• Anyone seen eASIC?, David R Brooks
  • Re: Anyone seen eASIC?, Austin Lesea
    • Re: Anyone seen eASIC?, PeteS
• timing constraints properly setup, axr0284
• WANTED: FPGA Development Board w/ Virtex-4 LX160/200 and 2 10/100 Ethernet PHYs, Frank
  • Re: WANTED: FPGA Development Board w/ Virtex-4 LX160/200 and 2 10/100 Ethernet PHYs, Brian Drummond
  • Re: WANTED: FPGA Development Board w/ Virtex-4 LX160/200 and 2 10/100 Ethernet PHYs, John Adair
• dynamically created blockRAM contents?, matteo
  • Re: dynamically created blockRAM contents?, Jim Wu
    • Re: dynamically created blockRAM contents?, matteo
  • Re: dynamically created blockRAM contents?, Symon
  • Re: dynamically created blockRAM contents?, KJ
    • Re: dynamically created blockRAM contents?, matteo
• Spartan3E minimum clock-to-output (hold time), Lars
  • Re: Spartan3E minimum clock-to-output (hold time), Lars
    • Re: Spartan3E minimum clock-to-output (hold time), Symon
    • Re: Spartan3E minimum clock-to-output (hold time), Bob
      • Re: Spartan3E minimum clock-to-output (hold time), Lars
      • Re: Spartan3E minimum clock-to-output (hold time), John_H
  • Re: Spartan3E minimum clock-to-output (hold time), Nico Coesel
    • Re: Spartan3E minimum clock-to-output (hold time), Peter Alfke
      • Re: Spartan3E minimum clock-to-output (hold time), Nico Coesel
• Altera Cyclone II die revision?, Manfred Balik
  • Re: Altera Cyclone II die revision?, Subroto Datta
• ISE 8.2sp3 clobbering source file timestamps?, Brian Davis
  • Re: ISE 8.2sp3 clobbering source file timestamps?, Lars
    • Re: ISE 8.2sp3 clobbering source file timestamps?, Brian Davis
• Re: How to deal with the negative value, Tom J
  • Re: How to deal with the negative value, Tom J
• LatticeMico32 Problem, Joel
  • Re: LatticeMico32 Problem, Jon Beniston
    • Re: LatticeMico32 Problem, fpgaman
• Unconnected Blocks??, idp2
• Virtex 4 FIFO question, John
  • Re: Virtex 4 FIFO question, John
    • Re: Virtex 4 FIFO question, idp2
      • Re: Virtex 4 FIFO question, idp2
  • Re: Virtex 4 FIFO question, Brad Smallridge
    • Re: Virtex 4 FIFO question, Peter Alfke
• Re: better ways for debugging?, CMOS
• Re: SUNDANCE FPGA CONFIGURATION, Martin Thompson
  • Re: SUNDANCE FPGA CONFIGURATION, Pablo
    • Re: SUNDANCE FPGA CONFIGURATION, Martin Thompson
• measure setup and hold time, axr0284
  • Re: measure setup and hold time, Lars
    • Re: measure setup and hold time, axr0284
      • Re: measure setup and hold time, Lars
      • Re: measure setup and hold time, axr0284
  • Medwedjew - who was that guy?, backhus
    • Re: Medwedjew - who was that guy?, Brian Drummond
• [XST 8.2.3] DSP48 inference multiply/add, Tim Verstraete
  • Re: [XST 8.2.3] DSP48 inference multiply/add, Jonathan Bromley
    • Re: [XST 8.2.3] DSP48 inference multiply/add, Tim Verstraete
      • Re: [XST 8.2.3] DSP48 inference multiply/add, Tim Verstraete
• Re: Tools available to split the design into multiple FPGAs., subint
• FPGA ROUTING, Ray
  • Re: FPGA ROUTING, Peter Alfke
    • Re: FPGA ROUTING, Ray
      • Re: FPGA ROUTING, JJ
  • Re: FPGA ROUTING, vasile
    • Re: FPGA ROUTING, vasile
    • Re: FPGA ROUTING, Symon
• Mapper using wrong EMAC with PowerPC in V4FX60, dcaulfield
• newbie needs help, Olivier Scalbert
  • Re: newbie needs help, Peter Alfke
  • Re: newbie needs help, John_H
    • Re: newbie needs help, PeteS
    • Re: newbie needs help, Olivier Scalbert
  • Re: newbie needs help, Olivier Scalbert
    • Re: newbie needs help, Jonathan Bromley
      • Re: newbie needs help, Olivier Scalbert
• Chipscope, nana
• xilinx spi example under linux, cpope
  • Message not available
    • Re: xilinx spi example under linux, Dave
      • Re: xilinx spi example under linux, Peter Ryser
• Using Altera's SerialLite to create a high-speed data link between Two or more FPGA's, jjlindula@xxxxxxxxxxx
  • Re: Using Altera's SerialLite to create a high-speed data link between Two or more FPGA's, jjlindula@xxxxxxxxxxx
• Spartan3 XC3S400 won't work after upgrading ISE from ISE6.3 to ISE8.2, jetq88
  • Re: Spartan3 XC3S400 won't work after upgrading ISE from ISE6.3 to ISE8.2, bjzhangwn@xxxxxxxxx
• Re: ERROR:NgdBuild:604, Guru
  • Re: ERROR:NgdBuild:604, Venu
    • Re: ERROR:NgdBuild:604, Guru
• PPC cache errata, Guru
  • Re: PPC cache errata, cpmetz@xxxxxxxxxxxxxx
    • Re: PPC cache errata, Ben Jackson
    • Message not available
      • Re: PPC cache errata, Guru
      • Re: PPC cache errata, cpmetz@xxxxxxxxxxxxxx
      • Re: PPC cache errata, Guru
      • Re: PPC cache errata, Erik Widding
      • Re: PPC cache errata, cpmetz@xxxxxxxxxxxxxx
      • Re: PPC cache errata, Brian Drummond
• FPGA-CPU THROUG ETHERNET, Pablo
  • Re: FPGA-CPU THROUG ETHERNET, Jon Beniston
    • Re: FPGA-CPU THROUG ETHERNET, Venu
• Re: Xilinx ISE 8.2.3 - Re-Creating Projects, Daniel O'Connor
• Wishbone I2C Application, camel_1213
• EDK 8.2 bidir gpio in XBD (board definition), Eric Smith
  • Re: EDK 8.2 bidir gpio in XBD (board definition), Eric Smith
• Xilinx: Connecting an on-chip memory-like component to Microblaze, Tom J
  • Re: Xilinx: Connecting an on-chip memory-like component to Microblaze, Tom J
  • Re: Xilinx: Connecting an on-chip memory-like component to Microblaze, Siva Velusamy
    • Re: Xilinx: Connecting an on-chip memory-like component to Microblaze, Tom J
      • Re: Xilinx: Connecting an on-chip memory-like component to Microblaze, Siva Velusamy
      • Re: Xilinx: Connecting an on-chip memory-like component to Microblaze, Tom J
      • Re: Xilinx: Connecting an on-chip memory-like component to Microblaze, Tom J
  • Re: Xilinx: Connecting an on-chip memory-like component to Microblaze, Jeff Cunningham
    • Re: Xilinx: Connecting an on-chip memory-like component to Microblaze, Tom J
• ISE Simulator radix question, Fred
  • Re: ISE Simulator radix question, Mike Treseler
    • Re: ISE Simulator radix question, Fred
      • Re: ISE Simulator radix question, Xiaqing Wu
      • Re: ISE Simulator radix question, Fred
  • Re: ISE Simulator radix question, Duth
    • Re: ISE Simulator radix question, Fred
• Re: SPI Flash on Avnet Spartan 3E Eval Kit, patrice . ulrich
  • Re: SPI Flash on Avnet Spartan 3E Eval Kit, Bill Burris
• Strange JTAG TCK problems with Spartan XC3S400, Ulrich Bangert
• lead free bga pads, colin
  • Re: lead free bga pads, PeteS
    • Re: lead free bga pa