Re: gpio help...

"Dave" <starfire151 AT cableone DOT net> schrieb im Newsbeitrag
news:12fm5ti6ptenffc@xxxxxxxxxxxxxxxxxxxxx

"Antti" <Antti.Lukats@xxxxxxxxxx> wrote in message
news:1157277138.918019.21750@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Dave schrieb:

I've got a ML403 Virtex 4 development board with an FX12 part on it.
I've
developed several VHDL components that I need to interface to an
embedded
MicroBlaze. The VHDL components interface to the outside world through
FPGA
pins. I've looked at some Xilinx examples of devices like LEDs and
switches
interfacing to the MicroBlaze but these devices are always defined
during
the Base System Builder in XPS. I've tried the process of adding a GPIO
for
32-bit input as:

1. Add IP for GPIO
2. Attach the GPIO to the OPB
3. Set the port connection IP2INTC_Irpt to opb_gpio_IP2INTC_Irpt
4. Set GPIO_in to opb_gpio_0_in
5. Generate addresses

Do the GPIO pins have to be mapped to FPGA I/O pins? I had to select
"Make
External" on each connection or I got errors when trying to build the
project.

How do I attach local component functionality (known only to the
top-level
VHDL) to these GPIO pins?

Are there any __simple__ examples of GPIO usage and instantiation with
connections to the top-level architecture?

Any help would be very much appreciated.

Thanks.

Dave

Dave,

first of all, it makes sometimes sense to learn by doing and trying.
sure you get mistakes and have to retry but you learn for good.

the _IN ports are used only if the GPIO is not configured as bidir read
the datasheet !

if you want to use the pins as external you sure nead to make them
external and the you also need to add the LOC constraints into the UCF
file.

as soon as that is done you can access the GPIO_in as inputs by simply
reading the GPIO base address

regarding you question about the toplevel entity, I dont understand
what you are talking about. if you work in XPS then its all there for
you and there is nothing to worry about, you do as explained above and
you get an functional SoC design that works.

if you want to use the EDK system as module as 'submodule' in ISE as
toplevel then that is another topic. but for starters I suggest you
work a little while with XPS only.

Antti
http://xilant.com

Hi Antti -

Thanks for taking the time to respond.

I agree entirely that it's usually good to use trial-and-error as a
training aid. But it only works if you eventually start making some
repeatable progress, which has not been my case. I've been trying for a
couple of weeks and have not made any progress. The GPIO-related
documentation included in the XPS does not address how to map the GPIO to
another component included in the design.

My project includes several VHDL components which have been included on a
top-level ISE project. These components serve as the interface to the
outside world to and from the FPGA. Some of these components are
inherited from other projects. They do some manipulation and conditioning
on the inputs from the outside world before making them available to the
MicroBlaze. The MicroBlaze component is included as a subcomponent of the
top-level system. Its purpose is to process conditioned inputs, store
them in some local registers, and send an output to a component which
further conditions the data then outputs it to the outside world. It was
thought to use GPIO interfaces to the MicroBlaze and other VHDL
components. (I apologize if I'm not using the correct terminology)

I cannot simply write data to or read data from a GPIO port from the
MicroBlaze. The inputs and outputs go through conditioners. Since I have
to go through conditoners and the GPIO does not need to talk directly to
the outside world, my question is can I map the GPIO_IN port pins to the
conditoner output port pins without having to use actual FPGA pins?

A simple example of what I'm talking about would be a MicroBlaze system
with a 32-bit GPIO output port writing bits 0 and 1. A component defined
in the ISE top-level VHDL has a logic function of "anding" the 0 and 1
bits from the GPIO and generating a single output to the FPGA pin
interfacing to the real world. In this case, there is no need for the
GPIO pins to be mapped to the FPGA I/O pins. Is this possible? Is there
a simple example of something like this being done? Is there a better way
of doing this?

Thanks again.

Dave


Dave,

if you want to 'and' the outputs of the GPIO then you just use
'util_reduced_logic', connect the GPIO to the inputs and the single output
as output pin to externa world. simple as that.

if you want to some conditioner before the GPIO in then you can make a
'wrap' around the user logic, and after that wire the custom logic to
gpio_in and the real inputs to your logic to the outside world. both of
those are doable 100% in XPS without the need of the ISE toplevel.

if you want to try just create a vhdl file with 1 vector input port and 1
vector output port import it into XPS and try to wire it between GPIO_in and
external ports. if you want to use EDK system as ISE submodul, start new ISE
project add dummy toplevel, then in ISE right click, new source, and select
'embedded processor' this will create EDK project as submodule in ISE.
simple as that.

Now if you want to wire some GPIO pins from the EDK into ISE toplevel and
not to IOBs you may need to look into the EDK toplevel wrapper (usually
system.vhd) you may need to remove the IOB prim instances there in order to
connect them succesfully in the ISE toplevel.

belive me, it all really 'just works' !

the only thing that may cause trouble are the extra io prims in the
system.vhd - so you need either modify it once per hand or make your owm. as
this file gets generated by XSP you need to have a custom duplicate of it.

Antti


.

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