Re: placing addiional caps across existing caps to reduce noise

On 27 Aug 2006 20:39:49 -0700, "rickman" <gnuarm@xxxxxxxxx> wrote:

Austin Lesea wrote:
To the subject at hand: placing additional caps across existing caps
does not reduce the noise (unless the dominant cause is lack of adequate
capacitance).

The reason why the noise is bad is that the L (as in Ldi/dt) is most
likely the largest, and most dominant factor, in the form of the via and
traces to the bypass capacitor.

Many times people have placed additional caps on top of the the existing
caps and wondered why the noise is not reduced: well, you did not
change the L in the equation, did you. So why did you expect V to change?

You may have moved the resonant frequency (more often not), but often
people make the mistake of assuming that a 0.1uF requires a 0.01uF and a
0.001uF in parallel. You can see that if the series L is dominant, you
haven't even moved the frequency by more than a few percent by the small
amount of additional capacitance.

What do you think about the idea that if the caps are connected
directly to good low impedance power planes that the location of the
caps are not critical at all. I have been discussing this in
comp.arch.embedded and have not gotten much negative feedback except
some claim that more is always better and that multiple values are not
needed.


I sometimes add a few SMA connector footprints to multilayer boards so
I can TDR the planes. As near as I can measure with my Tek 20 GHz TDR,
on a bare VME-sized (6U) board, good parallel planes look like an
ideal capacitor, with no evidence of edge reflections or anything like
that. And as you load ceramic bypass caps *anywhere* on the board, the
value of the ideal cap increases. So it doesn't much matter where you
put bypass caps.

The planes are a better cap than any discrete parts. Keep the
powerplane to ground dielectric thin, 5 mils or less, to keep the
plane capacitance high.

John


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