Re: behavioral vs post-P&R simulation mismatch

From: "tullio" <tullio.grassi@xxxxxxxxx>
Date: 31 Aug 2006 08:23:30 -0700

KJ ha scritto:

"tullio" <tullio.grassi@xxxxxxxxx> wrote in message
news:1156946690.228935.57540@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

I found the problem, it was actually in the signed logic.

<snip>

PS: Xilinx should give a bonus to users for finding their bugs...
Plus I could not find good guidlines on how XST interpret signed logic.

Opening a service request to Xilinx would be a good first step. Even now
that you 'know' the solution, Xilinx doesn't know about it until you let
them know through some mechanism.

KJ

yes i mentioned to a xilinx support guy.
Anyway I went on to test the compatibility with the Verilog standard of
ISE and ModelSim of other signed syntax. I found another violation of
XST. If you do:

output reg [10:0] UregU;
....
UregU <= $unsigned(-4);
// 11111111100 behav with ModelSim, correct;
// 00000000100 post-PAR (XST violates IEEE P1364-2005/D3)

.

References:
- behavioral vs post-P&R simulation mismatch
  - From: tullio
- Re: behavioral vs post-P&R simulation mismatch
  - From: Andreas Ehliar
- Re: behavioral vs post-P&R simulation mismatch
  - From: tullio
- Re: behavioral vs post-P&R simulation mismatch
  - From: KJ

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