Re: placing addiional caps across existing caps to reduce noise

David Brown wrote:
rickman wrote:
David Brown wrote:
Thanks for taking the time explaining this - between you and Symon I'm
hopefully learning something!

I had written a reply to this post, but I hit a wrong button as I typed
and POOF! So here it is again...

However, I've a couple of issues here. First off, I can't see that the
power planes have much capacitive effect at these frequencies (the
"planes" being polygons, with other signals on the same layer, and thus
having plenty of gaps). But I'll happily admit to not having a clear
idea how to model such planes or polygons.

If your planes are not designed to have good capacitance, then they
won't. They need to be complete on thier own layer and closely spaced.
It is not hard to get nFs from planes with very low inductance.


Secondly, I understand about different caps working better at different
frequencies, and obviously have bulk capacitors for the lower
frequencies (electrolytics near the regulators, and a few 4.7uF ceramics
around the board). But I still can't find any reason to expect a 0.001
uF ceramic 0603 capacitor to be significantly better at higher
frequencies than a 0.1 uF ceramic (same dialectric) 0603 capacitor.

It is not just that the caps work at different frequencies, it is how
they work with the power planes. A cap closely coupled to the power
planes will have a resonance (or anti-resonance) which will create a
*higher* impedance in that range of frequencies than either the cap or
plane alone. If you pick a cap of small value and low Q (high ESR) it
will have a low amplitude resonance, high in frequency. This same cap
will require a lot of them to provide effective coupling at lower
frequencies. So you can then use a smaller number of larger value caps
to provide a lowered impedance at lower frequencies. Again it is
important to not use parts with a high Q as this will raise the
amplitude of the impedance peaks due to parallel resonance. By using a
range of cap values the impedance is kept low across a wide range of
frequency and the resonances are kept to a minimum.


I'm now beginning to get a better idea of the parallel resonance
problem. In particular, it's the high Q of the plane capacitor that
causes the biggest issue.


Using the muRata software, I picked a 0603 X7R 100 nF capacitor. The
software gives it an SRF of 21 MHz, L of 0.63 nH, R of 0.027 O, and an
impedance of 0.14 ohm at 10 MHz, 0.02 ohm at 20 MHz, 0.16 ohm at 50 MHz,
0.38 ohm at 100 MHz, 0.78 at 200 MHz, and 1.97 ohm at 500 MHz. Picking
a 10 nF cap with the same setup gives an SFR of 67 MHz, and impedances
at these frequencies of 1.66, 0.77, 0.16, 0.24, 0.71 and 1.95 ohms. In
other words, it is a better at around 100 MHz, but not vastly better.
Until we start looking at special 0306 caps for frequencies of several
hundred MHz, I just don't see the benefit of smaller capacitance values.
Even then, it is more economical to simply use a few extra caps of the
same type (assuming the board has space for it).

But this does not take the parallel resonance into account. If
parallel resonance did not matter we could decouple everything with a
few tantalum caps.


You're right - I've been looking at the capacitors separately rather
than how they affect each other.

The card is not nearly as advanced as many of the cards made by people
in this group - it's highest frequencies are in the 150 MHz range, with
relatively few fast traces (there is a databus to an sdram chip, but the
only lines I really have to be careful with are the clocks to the sdram
chips at 75 MHz), and everything is fairly low power.

What you (and Symon) have given me is a number of ideas about the
problems on higher speed cards, and possible solutions to the problems,
along with a better understanding of what I don't know and need to learn
about if I am ever involved in making faster cards. I'm not a
specialist in this field (I'm mainly an embedded programmer), and know
that cards using the bigger and faster FPGAs would be completely out of
my depth, but I appreciate the tips I pick up here for my cards anyway.


It doesn't even take that many caps - I've got about a dozen for the
processor (which as two main supplies and a PLL supply), two or three
for each of the sdram chips, and one or two for each of the other major
chips.

It sounds like this is a simple design, but have you tested worse case?
Try the situation where the address and data bus both change from all
0s to all 1s at the same moment (assuming this processor can do that).
The DSP I last designed with would switch both data and address busses
at the same time. Put a high speed scope probe (with a very short
ground) on a separate output from this part that is set to a 1 and
watch the glitch, that is your total bounce including the inductance
from the power pins and the plane bounce. Also measure the glitch on a
power pin and you will have just the power plane noise. After you
consider this noise and the other sources such as crosstalk, can you
tell if your design is quiet enough. Testing won't do it unless you
explicitly test your worst cases.


I've done some worst-case (or close to worst case) testing of the
databus, but it would probably be a good idea to do some better
measurements during such tests.


One thing that makes a significant difference is that I'm not driving
any fast, high current lines - signalling is (almost) all TTL levels.
Higher current drives would mean more capacitors, but I'd still expect
to use the same types.

If you are driving with fast edges, you are driving high current.
Series terminated 3.3 volt CMOS driving a 50 ohm transmission line will
drive 33 mA per line. It will be much higher if it is not series
terminated. Multiply that by 64 and you get 2 Amps! Did you consider
this much current in your decoupling calculations? If you don't supply
the current from the power plane the caps can't really keep up with the
fast rise time of many drivers (< 1 ns). It will create high noise on
the planes and can trigger bounce logic level problems.


I've done some rough calculations, but the drivers are not that fast -
although I appreciate the levels of the current spikes. I have not seen
any indications of noise problems or bounce, but perhaps I need to do
some more careful measurements.

If you are using an MCU with fully internal memory then we are talking
about a different class of design and you can get by with a dozen or so
of single value caps.


The memory is not internal on this MCU, but I agree it's a different
class to designs using much higher speed devices and signals. I'm not
overly concerned about this design, but perhaps future cards will have
DDR memory and need more care.

Do you know the edge rate of your drivers on the SDRAM interface? They
are likley sub-nanosecond which means you need to consider both the SI
issues and the power distribution issues. It was not that long ago
that many PC motherboards could not work correctly with a third or
fourth SDRAM module plugged in because they did not do their homework
on SI issues. Now we are up to DDR2 speeds and are seeing the same
problems. But that does not mean you can ignore SDRAM SI issues. The
circuits are still the same and the edge rates can get you if you don't
give them their proper attention.

If you have a working board you can measure the ground/power bounce
rather easily. I think I described it before, but here it is again.
Write code to switch all the data bus and address bus signals in the
same direction at one time. Set some other output near these pins to a
constant level. Watch this constant output and see if you get a glitch
on this pin when the others change. This is the amplitude of the
bounce on your device. There may be additional noise on the
power/ground planes that comes from other chips so this may not be the
worst case noise the chip will see.

On a separate note, I can't believe some of the things we do here. Our
digital circuits are part of RF equipment so we are typically very
concerned with even low levels of noise in the RF region. To make sure
our boards are quiet we have an RF person review the design and board
layout. I was assisting on a design for a simple MCU board with an
attached GPS receiver. The RF guy was very concerned about various
noise sources that had burned him in the past and did a lot of what I
thought was overkill in the power distribution. I just found out that
he had the 6 layer stackup done with two ground planes and no power
plane! I suggested to the layout guy that it would be ok to flood fill
the signal layers with power plane and he said they are doing that, but
connecting to ground instead of power!!! So there is no effective
bypassing on this board above a couple hundred MHz and the freq of the
receiver is around 1.5 GHz. Do you think we will see any interference?

.

Relevant Pages

  • Re: placing addiional caps across existing caps to reduce noise
    ... power planes have much capacitive effect at these frequencies (the ... "planes" being polygons, with other signals on the same layer, and thus ... It is not just that the caps work at different frequencies, ... I just don't see the benefit of smaller capacitance values. ...
    (comp.arch.fpga)
  • Re: placing addiional caps across existing caps to reduce noise
    ... Placement is not critical, as ... long as you have via in pad, and planes. ... back to the chip through the power pins. ... I can't say a design failed because of low loss caps, ...
    (comp.arch.fpga)
  • Re: placing addiional caps across existing caps to reduce noise
    ... an individual chip pwr/gnd couples to those planes, ... coupled in parallel to the users PCB power planes. ... largely depend on the inductance of the connection and I expect you ... Adding caps or planes to the package ...
    (comp.arch.fpga)
  • Re: PCB Bypass Caps
    ... the highest frequencies where caps are too high impedance to do much ... So don't skimp on the planes, keep them as large as possible. ... In the end you may need to add a second power layer or mix power and ... while the capacitance is larger to have 100 sqare inches ...
    (comp.arch.fpga)
  • Re: Doubt about decoupling capacitors in high-freq PCBs
    ... >> caps to cut cost. ... >ground planes for digital circuits. ... plane and power planes it doesn't matter much ... bypasses anywhere just makes it look like a bigger ideal capacitor. ...
    (sci.electronics.basics)