MPMC2 : npi issues

Hi,

I am exploring the possibility to use the npi(native port interface) towards the MPMC2(multi port memory controller). I will use the BRAM as FIFO on the write side of the RAM

Does anyone have any experience with this ? After reading the documentation(http://www.xilinx.com/esp/wired/optical/xlnx_net/mpmc2/ug253.pdf) I am left with a lot of questions. I am not able to find any other documentation/user experience.

I want to use the timing as described in figure 37: Word write

My main questions are:

1. How long can the delay between AddrReq and AddrAck be ? If this can be of arbitrary length(as claimed in the documentation) one need to buffer the data before the npi to ensure not to loose data.

2. Our memory has 32 bits datalength, while npi uses 64 bits. How is the data alignment between this two busses ?

Any comments/answers will be greatly appreciated !
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