Re: behavioral vs post-P&R simulation mismatch


"tullio" <tullio.grassi@xxxxxxxxx> wrote in message
news:1156946690.228935.57540@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
I found the problem, it was actually in the signed logic.
<snip>
PS: Xilinx should give a bonus to users for finding their bugs...
Plus I could not find good guidlines on how XST interpret signed logic.

Opening a service request to Xilinx would be a good first step. Even now
that you 'know' the solution, Xilinx doesn't know about it until you let
them know through some mechanism.

KJ


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