Re: placing addiional caps across existing caps to reduce noise

"David Brown" <david@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message
news:44f59085$1@xxxxxxxxxxxxxxxxxx

Thanks for taking the time explaining this - between you and Symon I'm
hopefully learning something!

However, I've a couple of issues here. First off, I can't see that the
power planes have much capacitive effect at these frequencies (the
"planes" being polygons, with other signals on the same layer, and thus
having plenty of gaps). But I'll happily admit to not having a clear
idea how to model such planes or polygons.

Secondly, I understand about different caps working better at different
frequencies, and obviously have bulk capacitors for the lower
frequencies (electrolytics near the regulators, and a few 4.7uF ceramics
around the board). But I still can't find any reason to expect a 0.001
uF ceramic 0603 capacitor to be significantly better at higher
frequencies than a 0.1 uF ceramic (same dialectric) 0603 capacitor.

Using the muRata software, I picked a 0603 X7R 100 nF capacitor. The
software gives it an SRF of 21 MHz, L of 0.63 nH, R of 0.027 O, and an
impedance of 0.14 ohm at 10 MHz, 0.02 ohm at 20 MHz, 0.16 ohm at 50 MHz,
0.38 ohm at 100 MHz, 0.78 at 200 MHz, and 1.97 ohm at 500 MHz. Picking
a 10 nF cap with the same setup gives an SFR of 67 MHz, and impedances
at these frequencies of 1.66, 0.77, 0.16, 0.24, 0.71 and 1.95 ohms. In
other words, it is a better at around 100 MHz, but not vastly better.
Until we start looking at special 0306 caps for frequencies of several
hundred MHz, I just don't see the benefit of smaller capacitance values.
Even then, it is more economical to simply use a few extra caps of the
same type (assuming the board has space for it).

It doesn't even take that many caps - I've got about a dozen for the
processor (which as two main supplies and a PLL supply), two or three
for each of the sdram chips, and one or two for each of the other major
chips.

One thing that makes a significant difference is that I'm not driving
any fast, high current lines - signalling is (almost) all TTL levels.
Higher current drives would mean more capacitors, but I'd still expect
to use the same types.


Hi David,
I think the main issue at stake in this thread isn't the impedances per se,
but resonances between the various components of the board assembly. I
recommend that you try using spice simulations to see these resonance
mechanisms for yourself. This certainly increased my understanding of the
subject. The LTSpice files I posted might help get you started.

In summary, I think we have (at least) two different methodologies in this
thread.

1) Rick's teacher has presented a way to prevent resonances between bypass
caps and power planes. These resonances can be substantial because of the
high Q of the plane capacitance. He prevents this serious resonance by using
a bunch of different valued capacitors to move and spread out the resonance.
This introduces new parallel resonances between these different valued caps,
but these aren't as bad as the original plane resonance because the caps
have low Q.

2) For FPGA boards, I suggest a solution whereby we dispense with the power
plane. Hence no serious resonance, as we have no high Q components. Use one
value of decoupling cap to prevent resonances between different values. Pick
a value with crappy Q. We have lost the very high frequency decoupling
capability of the plane capacitance, but that was no use anyway as we can't
couple this plane capacitance to the device we're using because its package
has too much inductance (from its balls and vias plus the PCB vias).
Instead, we use a bunch (maybe even a bigger bunch than in (1)) of bypass
caps (very) near the device and a small 'mini-plane' to parallel them
together. The money you've saved by removing a PCB layer pays for the extra
caps.

Both methods will work. Each has pros and cons. But I use methodology 2).
:-) As package technology advances, I will re-evaluate this position. I may
also need to learn how to use a 3-D modelling package, as lumped simulation
is not much help beyond 1GHz.

Cheers, Syms.
p.s. In both methods, the over-riding key issue is to have a decent ground.
Without that, forget everything.


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