Re: placing addiional caps across existing caps to reduce noise


Symon wrote:
OK, I think you're correct, this conversation has reached an end. It can go
nowhere with one of us posting data and sims (including ones that model the
power planes, albeit as a lumped capacitance) that the other cannot or will
not look at, the other posting hearsay from a class he went to. I will,
however, try to make one last point based on the snippet above.

Probably, but I also think this topic should probably be revisited from
time to time as well. As Austin stated in the intro post, there are few
reasons to stack caps (unless the dominant cause is lack of adequate
capacitance), which simply shouldn't happen if you have a good idea
what worst case current spikes from the chip are. That unfortunately
isn't specified, because it's highly variable depending on the design,
place/route, and other factors. If something is "fixed" by adding some
additional medium/low speed capacitance, then you made some wrong
assumption, or have a process problem (like poor via plating as I've
seen before).

My experience is that there are some designs, which do not work in some
packages, even with best possible practice on the user PCB, simply
because of the inductance and resistances in the package. My REALLY BAD
experience was XCV2000E's in BG560's. I've had similar problems with
other parts that are not nearly as clear, but find comfort that Xilinx
is improving packaging so they believe that XC4V and XC5V should not be
a problem. When I have time, I may revisit the PCB layouts given your
wonderful enlightment, and see if there are improvements to be made.

Maybe I'll even risk getting a few XC4VLX100, XC4VLX200's, or XC5V
parts and giving it a try. I suspect there may still be some land mines
that are related to very dense designs which are optimized to one
combinatorial delay based around SRL's, with minimum inter LUT routing
dominating the timing and power requirements, and may result in very
short power bursts several times the average current. In the largest
parts, the clock skew may hide this, thus preventing the current
stackup. If it's possible to juggle the routing to balance the clock
skew, there may well still be "perverse" ways of getting the parts to
fail, that can also be accidentally invoked by placement and routing
variations. It would be interesting to spend a few days to verify this,
and see if it really is safe not to worry about unexpected worst case
stackups.

In the end, we may have to move to the next level, and get rid of the
packages all togather. When I asked Xilinx about getting raw tested die
for direct user PCB attach last year they were a very resistant. With
half, or better of the inductance still remaining in the package, it's
getting tougher, even with best practice, to meet the demands for high
performance applications.

thanks .. and Have Fun!!
John

.

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