Re: placing addiional caps across existing caps to reduce noise
- From: "John_H" <newsgroup@xxxxxxxxxxxxxxxx>
- Date: Tue, 29 Aug 2006 16:07:32 GMT
"rickman" <gnuarm@xxxxxxxxx> wrote in message
news:1156861074.825726.84320@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
I would love to see some data to support that statement about the lower
inductance. I don't have Ritchey's book handy, but I seem to recall
that moving the vias from the end of the pads to the side was only a
small delta in total inductance (significantly smaller loop area). I
expect that moving them to the center would be another small delta.
This has to be considered in the context of both the inductance of the
device itself as well as the result on the impedance of the board.
I think you will find that small changes in inductance do not have a
major effect on the utility of the caps. If you use multiple caps with
mutiple values you can get a low impedance over a wide bandwidth with a
minimum number of caps. I have no doubt that using via in pad will
help to raise the resonant frequencies, but I think you will find that
if you do all the other things right it will not make much difference
in the end.
Won't any higher inductance result in the same above-SRF slope? That is,
given the total inductance, it won't matter what the capacitance is once
above an ohm in the impedance vs freq plot.
I've seen good information on Cadence tools based on Sun Microsystems work
that tracks what you've described with Ritchey. A recent Howard Johnson /
Xilinx talk also covered many of these items well without contradiction.
In each case, the lowest inductance achievable was always the goal. The
small deltas may be small in nanoHenrys but are probably a significant
percentage.
Same-side vias are better for a cap than end vias. Vias in pad are better.
Partial vias in pad are best. That's the understanding I got.
A distribution of capacitance can give a superb, flat impedance over a wide
frequency range. Resonance is a problem for low ESR caps too far apart in
frequency such that they cancel each other out with an LC resonance between
the SRFs of the two values. Vias in pads provide better performance.
.
- Follow-Ups:
- References:
- placing addiional caps across existing caps to reduce noise
- From: Austin Lesea
- Re: placing addiional caps across existing caps to reduce noise
- From: rickman
- Re: placing addiional caps across existing caps to reduce noise
- From: Austin Lesea
- Re: placing addiional caps across existing caps to reduce noise
- From: KJ
- Re: placing addiional caps across existing caps to reduce noise
- From: John_H
- Re: placing addiional caps across existing caps to reduce noise
- From: rickman
- placing addiional caps across existing caps to reduce noise
- Prev by Date: Re: UltraController II + SystemAce
- Next by Date: Re: Quartus software and dual-purpose pins
- Previous by thread: Re: placing addiional caps across existing caps to reduce noise
- Next by thread: Re: placing addiional caps across existing caps to reduce noise
- Index(es):
Relevant Pages
|
Loading