Re: Do I need to adjust sdram clk shift when i lower my system clock?
- From: "Gabor" <gabor@xxxxxxxxxxx>
- Date: 29 Aug 2006 06:23:35 -0700
Tony wrote:
Hi everyon, hope someone can give me a pointer or help.
I lowered the system clock in the Altera stratix example design
(standard) from 50 to 35 Mhz. Is it necessary to change the time shift
of the sdram clock?? (-3.5ns by default)
because, a time shift of -3.5 ns seems to work fine until i fixed a
huge (around 10k LE) jpeg decompression unit on to the system. Does
anyone know do i need a new time shift or not?
I tried a several delay from -1.0 to -8ns, but the system is still not
stable, my c program can be downloaded to the board but at times fails
to verification.
(It sometimes passes verification, but the program doesn't run
properly. To simplify debugging, I only put a printf statment in my
main(), but it doesn't print)
ps. I put my program and all data memory in sdram
Thanks
When adding a huge amount of switching logic to any design, errors
are very likely introduced by either placement or power supply droop.
If you have any unconstrained paths, the large addition can create
problems. However it is also likely that the additional power draw
of the jpeg decompression is causing issues. I would recommend
putting a scope on the power to make sure you're not getting a
significant voltage drop due to the increased switching.
Also when reducing the SDRAM clock, make sure you don't violate
the refresh period requirements. Normally refresh timing is done by
counting clock cycles, but the parts require refresh periods that are
not clock rate dependent, so you would need to reduce the number
of cycles between refreshes by the ratio of the clock rate reduction.
HTH,
Gabor
.
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