Re: placing addiional caps across existing caps to reduce noise
- From: "rickman" <gnuarm@xxxxxxxxx>
- Date: 27 Aug 2006 20:39:49 -0700
Austin Lesea wrote:
To the subject at hand: placing additional caps across existing caps
does not reduce the noise (unless the dominant cause is lack of adequate
capacitance).
The reason why the noise is bad is that the L (as in Ldi/dt) is most
likely the largest, and most dominant factor, in the form of the via and
traces to the bypass capacitor.
Many times people have placed additional caps on top of the the existing
caps and wondered why the noise is not reduced: well, you did not
change the L in the equation, did you. So why did you expect V to change?
You may have moved the resonant frequency (more often not), but often
people make the mistake of assuming that a 0.1uF requires a 0.01uF and a
0.001uF in parallel. You can see that if the series L is dominant, you
haven't even moved the frequency by more than a few percent by the small
amount of additional capacitance.
What do you think about the idea that if the caps are connected
directly to good low impedance power planes that the location of the
caps are not critical at all. I have been discussing this in
comp.arch.embedded and have not gotten much negative feedback except
some claim that more is always better and that multiple values are not
needed.
A recent SI/EMI class I took says that you can put a relatively small
number of caps pretty much anywhere on the board as long as they are
coupled to the power planes with no traces, just the via. This gives a
very low impedance connection to the planes and the planes give a very
low impedance connection to the chip. It was also shown that to get a
low impedance over a broad bandwidth multiple values are needed to push
the impedance down and the parallel resonance up. High loss capacitors
(X7R/X5R vs. C0G) were also recommended to reduce the signficance of
the parallel resonance.
Does any of this sound correct to you? It was sure convincing in the
class and appears to be a very sure way of getting low noise on the
power planes and thereby on the chip power pins!
.
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