Re: Why No Process Shrink On Prior FPGA Devices ?

Brannon,

That, and more.

Back when going from 1u, to .8u, to .65u, etc. was as simple as just
making a mask where everything was smaller, shrinking was just good
business. Cheaper parts, maybe even faster parts, same functionality.

But now, making something smaller is a complete re-design, with all
circuits getting completely re-simulated, and redone. And finally the
layout has changed such that a plain shrink would violate all the design
rules.

Basically, not an option anymore.

The last shrink we did was 0.18u to 0.15u in Spartan 2E for cost reasons
(years ago). It involved a lot of work, but just slightly less than a
completely new product, so it made sense.

Austin

Brannon wrote:
now if we would technology shrink some FPGA family then the amount
of work to be done for new 'characterization' of the silicon is
enourmous.

and if you know the mask set pricing then you can easily understand
that this is not an option for any FPGA vendor.

So let me conclude this to make sure I understand:

1. You cannot shrink FPGAs because when you shrink them, you have to
update all the design PAR files to match the new timing. 2.
Characterizing the timing on these internal lines is a pain in the
***. 3. Hence, nobody wants to invest that money when they could be
spending their time getting the timing right on their latest designs.

Sound right?

.