Re: Embedded clocks

rickman wrote:

Jim Granville wrote:

rickman wrote:
<snip>

If I am going to require a time reference at the receiver the simplest
scheme I know of is just async serial data with a start and a stop bit.

This is not quite the simplest.

It imposes clock tolerance requirements, and is half duplex, so the
Transmit has to generate it's own clock.


But if I have an oscillator, I have a clock available. That is my
point. RS-232 has very loose requirements for a clock. An RC may not
be good enough, but it doesn't take much.

anything better than RC, has starting time issues, so usually runs
all the time, and that has power penalties.


If you want to ease that, you can do something like the LIN bus, which
gives a auto-baud pre-amble, but that is getting complex for CPLDs.


Way too complex. I am looking at a very small package and I may be
limited to 64 logic cells. In fact I don't know that I can make this
work in such a small part. The problem is that one end of the link has
to be built into a cable housing where the signals are fanned out
again. I don't need a lot of IO, but I expect it will take more than
64 logic cells.



No point in using Manchester encoding if I am transferring the data
over a wire just a few inches long.

Many TV remote's use manchester, and they do that to allow the use of RC
clocks, and straight from battery operation.

If you want the simplest scheme, in a CPLD, use one-wire, because that
is duplex, and does not need to generate a TX clock, just a Tx time slot
( which can be monostable derived ).


I don't see one wire as being any simpler than a UART. One wire is
just bit async rather than byte async. You still need a timer to time
the bits.

build them both, and count the macrocells :)

UARTs need (commonly) /16 resettable counter on RX, and a /16 non resetable counter on TX, plus the byte buffers in both directions.

So that's at least 8 macrocells running higher than the bit-rate,
plus appx 4 more do do the framing, vs 3-4 for PWM bus.

PWM Osc is gated-monostable type at 4x bit rate - so power is lower.
A 3 bit Gray counter handles RxSample, TxWindow, and Sync detect

Simulating all this is not that easy, on today's tools, which are designed for a master-clock approach.


If you can get up to 2 wires, then i2c & variants are a widely used
standard, and it does not take too much CPLD resource.


Yeah, I have thought about I2C, but it would have to run at High Speed
to work properly due to the addressing overhead.

CPLDs have no problems with speed, but the host speed may be a stumbling
block. Philips talked about 3.4MHz i2c, but nothing seems to have hit the streets. I see they now have a FM+ spec, which is high drive i2c,
at 1MBd, also well within CPLD's reach.

i2c Address info can be compile-time-coded into CPLDs, to save pins
and macrocell resource.

SPI would work too, but would use all four pins leaving us no spares.

SPI can work with 3 wires, if that helps.

A UART interface could use two wires, one for transmit and one for receive.

The word
size can be application specific with dedicated bits for discrete
signals. Most importantly, I think it will be the smallest in a CPLD.

How many IO's do you need, on how many addresses ?

Do they need dataDirection register control, and read-back, or
are simpler fixed OUT and IN acceptable ?

64 Macrocells sounds plenty, could even manage this in 32 Macrocell parts.

-jg

.

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