Re: Embedded clocks



rickman wrote:
Frank Buss wrote:

rickman wrote:


Is self clocking on a single pin possible? I am thinking that the
extra info has to be presented in some manner that requires either a
timing or amplitude measurement.

As Jim wrote, the one-wire bus can do this. With this concept you need only
one wire (and ground) to power and communicate with a device:

http://pdfserv.maxim-ic.com/en/an/onewirebus.pdf
http://www.maxim-ic.com/appnotes.cfm/an_pk/126


Thanks to everyone for their posts. Each of the above solutions
require timing of the signal and so will not work without a clock (or
timer) of a specified rate. The key is "specified". To decode a
machester stream you need a time interval of about 3/4 of the bit time
in order to blank the edge detector on the edge between bits. That
interval can be somewhat broad, but must be known to at least better
than 33%. So I can't read a Manchester stream at 10 Mbps and one at 1
Mbps with the same timer. Of course I can design a circuit that will
synchronize the clock to a fixed rate bit stream. But that is a lot
more complex. I am looking for something that will just plain clock
the data across the interface without a requirement to know the
frequency whether by measuring it, or a priori.

Why do you need such a loose frequency spec ?

ALL schemes will clearly need some time-element.

What you need is to reduce the Clock _tolerance_ and _power_ costs, to
minimal levels.

The one-wire (PWM data) designs change from a classic clock (which draws power all the time ) to a more async-based monostable ( so can idle at very low powers ). It also drops the clock tolerance to quite slack levels, met by the cheapest components.
The overhead, is slightly less bandwidth efficency than other modulation
methods.

With one wire, the master provides the edges, and the slave the data (sometimes), and the slave can use very cheap / low power / fast wakeup RC oscillator.

one-wire designs are implicitly duplex, and so are better suited than manchester to low cost slave nodes.

They also work well with CAN transcievers, as that is a 'OR' BUS

-jg



.



Relevant Pages

  • Re: 96 cabrio possible electrical prob?
    ... > circumstances the clock has been reset. ... so it's apparently not a system-wide power outage going on here. ... way to stop the clock is to disconnect this wire. ...
    (rec.autos.makers.vw.watercooled)
  • Re: [linux-pm] Power Management framework proposal
    ... this API is not trying to represent the parent-child hierarchy. ... That is not part of the fw: the fw simply expresses parent-child clock ... The very same idea of power mode is something that can maybe fit some ... kernelspace or strictly userspace. ...
    (Linux-Kernel)
  • Re: Source of Dynamic Power Consumption in FPGAs
    ... In CMOS devices the power consumed comes from charging and discharging ... So I would expect the clock trees with their constant ... Second on my list is the routing since I would expect the capacitance ... If the registers are placed at the input to a function block the ...
    (comp.arch.fpga)
  • Re: [linux-pm] Power Management framework proposal
    ... the clock framework? ... capable drivers having another, embeded devices presenting a third, etc ... the user of this API doesn't care how something is done, it just wants to know what's possible and how to tell the system to switch modes. ... this is more then just setting the clocks on everything becouse some power modes are not easily represented just as clocks. ...
    (Linux-Kernel)
  • Re: The real twin paradox.
    ... Sue, on the other hand, claims that the traveling twin's clock ... I may give up drinking water because the pipes ... The light in an AC power cord does not weigh much so it ... You can be wrong and the capacitor banks still be required. ...
    (sci.physics.relativity)