Re: Switching two (synchronous) clocks with variable phase difference, without glitching or period loss

Wow, three Peters in various stages of disagreement...
I suppose it depends on the basic assumptions.
In "6 easy...", I assumed a worst case, where the switching is
asynchronous, and the two clocks have no known phase of frequency
relationship.
In today's posting the two frequencies are identical, but the phase
relationship is unknown. Let's assume the decision to switch is
synchronous with the presently used clock. Then you have to make sure
that the to-be-acquired rising clock edge is at least a clock period
later (otherwise I can get in timing trouble). That assumption
inherently loses one clock transition (except in the extreme case when
both phases are aligned.
If you change the rules, and acept a shorter clock cycle during the
switch-over, things are different, but you now must put a limit on it,
otherwise you get two clock edges that are very close (and how close is
too close ?)
That's why I wrote my skeptical remarks.
Back to the Peters
Peter Alfke.
=====================
PeteS wrote:
Peter Alfke wrote:
Peter,
the way you describe your problem, there is (and there can be) no
solution, if you switch asynchronously between two unknown clocks.
You will lose an edge, since you cannot use edges that are very close
to each other.
Assume the two rising edges are 50 ps apart. Are they two edges or one?
How's about 1 ns, etc.?
You must be willing to lose an edge, and the"six easy pices" circuit is
your solution.
Cheers
Peter Alfke, Xilinx
==================
PeterC wrote:
I have two clocks which are relatively synchronous (ie. the frequencies
are exactly the same because the originate from the same master clock),
but one of the clocks is shifted in phase, and this phase shift is
dynamically variable and may be up to one whole period.

I need to switch between these two clocks, but without losing rising
edges. From my experiments with BUFGMUXs, I appear to be losing a
rising edge (post PAR timing simulation).

I believe Peter's circuit in his Six Easy Pieces may also cause an edge
to be lost. Peter writes "Any clock-switching starts when the
originally selected clock goes Low, and the Output Clock then stays Low
until the newly selected clock has first gone Low and then High again."

I realize that asynchronous clock multiplexing has been covered many
times in the group, but I simply can't find a good solution to my
specific problem.

Peter.

Hi Peter

As much as I dislike disagreeing with the renowned Peter Afke, one can
switch between two asynchronous clocks (in this case as the frequencies
are locked but the phase differs, and can change).

I once designed a hitless switch (in telecom, for DS3) to switch
between two source synchronous bit streams, with a phase asynchronicity
attributable to path delay which was variable, that did not miss a bit
during switching between space diversity receivers (hence hitless :)

That's important in DS3, of course, as missing a bit has a major hit on
framing, so frame relock is then necessary, which was deemed
unacceptable.

It takes a little work but can be done. In that case, I conditioned
both the clocks _and_ the data stream (which could have a significant
bit position offset), which may be overkill here.
Without knowing more about the specifics of PeterC's requirements,
(both for clock rates and phase rate of change apart from overall
structure) it's hard to be specific. I will also mention I used
discrete and analog techniques (ECL for the logic) - this was in the
days before really fast VLSI (or even really fast LSI for that matter,
excepting ECL), but the same techniques could be used simply transposed
completely into the digital domain.

Maybe I'll chew over it over the next couple of days, run up some code
over the weekend and post it (warning : I prefer Verilog ;)

Maybe :)

Cheers

PeteS

.

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