Re: Problems compiling with ISE Webpack 8.2.01i

Hello Duane.
Thanks for the feedback. I have tried to rewrite the program and
correct the errors which were there in the original one.The program
here is the same one as before i.e. it counts the number of ones in the
bit stream. The only problem im facing now I can't really understand
the library inclusion stuff in modelsim. If my physical name differs
from the logical name then in the workspace window I actually see two
libraries named after them whereas if the names are the same then
theres just this one library called work(provided both of them have
been called 'work'). Additionally it seems possible to create a working
model without having to include it in a project. It is done by creating
a directory and mapping the local primary library i.e. work to it which
seems a little too strange to me. ...so to load those files you have
to "load that directory"
Heres the code:

library work;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.ALL;

entity ones_cnt is
Port ( A : in BIT_VECTOR (2 downto 0);
C : out BIT_VECTOR (1 downto 0));
end ones_cnt;

architecture Algorithmic of ones_cnt is
begin
process(A)
variable NUM: INTEGER range 0 to 3;
begin
NUM := 0;
for I in 0 to 2 loop
if A(I) = '1' then
NUM := NUM + 1;
end if;
end loop;
case NUM is
when 0 => C <= "00";
when 1 => C <= "01";
when 2 => C <= "10";
when 3 => C <= "11";
end case;
end process;
end Algorithmic;

entity AND2 is
port (I1,I2: in BIT; O: out BIT);
end AND2;
architecture BEHAVIORAL of AND2 is
begin
O <= I1 and I2;
end BEHAVIORAL;

entity OR3 is
port (I1,I2,I3: in BIT; O: out BIT);
end OR3;
architecture BEHAVIORAL of OR3 is
begin
O <= I1 or I2 or I3;
end BEHAVIORAL;

--use work.all;
entity MAJ3 is
port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
end MAJ3;
architecture AND_OR of MAJ3 is
component AND2C
port (I1,I2: in BIT; O: out BIT);
end component;
component OR3C
port (I1,I2,I3: in BIT; O: out BIT);
end component;
for all:AND2C use entity Work.AND2(BEHAVIORAL);
for all:OR3C use entity Work.OR3(BEHAVIORAL);
signal A1,A2,A3: BIT;
begin
G1: AND2C
port map (X(0),X(1),A1);
G2: AND2C
port map (X(0),X(2),A2);
G3: AND2C
port map (X(1),X(2),A3);
G4: OR3C
port map (A1,A2,A3,Z);
end AND_OR;

entity AND3 is
port(I1,I2,I3: in BIT;
O: out BIT);
end AND3;
architecture BEHAVIORAL of AND3 is
begin
O <= I1 and I2 and I3;
end BEHAVIORAL;

entity OR4 is
port(I1,I2,I3,I4: in BIT;
O: out BIT);
end OR4;
architecture BEHAVIORAL of OR4 is
begin
O <= I1 or I2 or I3 or I4;
end BEHAVIORAL;

entity INV is
port (I : in BIT; O : out BIT);
end INV;
architecture BEHAVIORAL of INV is
begin
O <= not I;
end BEHAVIORAL;

entity OPAR3 is
port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
end OPAR3;
architecture AND_OR of OPAR3 is
component AND3C
port (I1,I2,I3: in BIT; O: out BIT);
end component;
component OR4C
port (I1,I2,I3,I4: in BIT; O: out BIT);
end component;
component INV1
port (I: in BIT; O: out BIT);
end component;
for all:AND3C use entity Work.AND3(BEHAVIORAL);
for all:OR4C use entity Work.OR4(BEHAVIORAL);
for all:INV1 use entity Work.INV(BEHAVIORAL);
signal A1,A2,A3,A4,NA0,NA1,NA2: BIT;
signal T0,T1,T2,T_out: BIT;
begin
T0 <= X(0);T1 <= X(1);T2 <= X(2);
I1:INV1
port map(T0,NA0);
I2:INV1
port map(T1,NA1);
I3:INV1
port map(T2,NA2);
G1: AND3C
port map (T2,NA1,NA0,A1);
G2: AND3C
port map (NA2,NA1,T0,A2);
G3: AND3C
port map (T2,T1,T0,A3);
G4: AND3C
port map (NA2,T1,NA0,A4);
G5: OR4C
port map (A1,A2,A3,A4,T_out);
end AND_OR;

architecture STRUCTURAL of ones_cnt is
component MAJ3C
port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
end component;
component OPAR3C
port (X: in BIT_VECTOR(2 downto 0); Z: out BIT);
end component;
for all: MAJ3C use entity MAJ3(AND_OR);
for all: OPAR3C use entity OPAR3(AND_OR);
begin
COMPONENT_1: MAJ3C
port map (A,C(1));
COMPONENT_2: OPAR3C
port map (A,C(0));
end STRUCTURAL;

configuration Trial of ones_cnt is
for STRUCTURAL
end for;
end Trial;

This code compiles properly and I do see the waveform that I am
supposed to see. I would like to know more about the libraries and the
..ini file and the _info file that gets placed into a folder called
'work' . I guess this work folder which doesn't contain anything except
this _info file which is like a pointer to the actual source files or
the directory where the simulator can find the files i.e. the local
directory.
Hope to hear from you,
Aijaz Baig.
Duane Clark wrote:
aijazbaig1@xxxxxxxxx wrote:
Hello Freinds.
I am a newcomer to the field of programmable logic devices and I am
currently trying to teach myself VHDL. I hope to learn some VHDL before
the next semester starts.
My sole purpose as of now is not to actually synthesise stuff but just
to simulate the various designs that I may try to create. I am using
the xilinx ISE webpack 8.2 on a windows XP machine.
Below I am trying to implement a design called ones_cnt wherein the
counter just counts the number of ones in a 4 bit array and prints the
result in a binary format.To understand the concept of configuration
declarations I have declared multiple architectures and I am trying to
use the configuration declaration statement to select one the them.

Heres my code. Its a lil big may be but I hope you guys would have a
look.


...
use work.all; ----- this is the line where the error is flaged!! see
below for details.


...
Heres the log report generated by the compiler:
Started : "Check Syntax".
Running vhpcomp
Compiling vhdl file "E:/Xlinx_ISE/workbench/ones_cnt.vhd" in Library
isim_temp.

I don't know where the library name isim_temp came from. Did you specify
that somewhere? The default name is normally "work" and it is generally
best to leave it that way.

If you really want to use a different name for some reason, then in the
line above that generates the error, you would want to change it to:
use isim_temp.all;

As mentioned, generally you always want to compile entities into a
directory named work. There is certainly no reason for a beginner to do
differently. Then, if the entities you are using are part of the current
project, the "use work.all;" will get them fine.

If you also want to use entities that were compiled elsewhere, that is
libraries, then you will have a file that provides a mapping. In
Modelsim, the file is named modelsim.ini, or project_name.mpf. I don't
know about the simulator you are using, but if it is not Modelsim, it
will have some similar process. There, it will map a library name used
in the current directory to the work directory where your library
actually is located:
[Library]
sse_mezz_lib = ../../sse_mezz/sseio_hdl/work
Notice that the library files are also compiled into a directory named
work, but it is a work directory in a different location from the
current project.

.

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