Re: Partial shift register extraction in ISE

Any register with a reset term should not infer SRL, since there
is no asynchronous (or synchronous) reset on distributed RAM.
So normally just adding the asynchronous reset process for the
pipeline stages and not for the slower stages should get the job
done. I've noticed that XST likes to use SRL whenever possible,
and it will warn you about large registers that don't fit into SRL
due to reset requirements.

Johan Bernspång wrote:
Hi all,

I'm building a design where I want ISE (8.1) to extract the shift
registers in some parts, i.e. where I have inferred SRL counters etc,
and not to extract them in other parts. For instance where I have coded
multiple stages of pipelining in order to obtain timing closure. Has
anybody done this? Partial shift register extraction, that is.

The design is occupying about 50% of a Virtex-2 2000 and running mostly
at 200 MHz. This is why I need to insert some pipelining between
different stages in the signal path. My intention is to add a few stages
to enable ISE to divide the routing in shorter bits.

Any input is highly appreciated

/Johan


--
-----------------------------------------------
Johan Bernspång, xjohbex@xxxxxxxx
Research engineer

Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems

www.foi.se

Please remove the x's in the email address if
replying to me personally.
-----------------------------------------------

.

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