Re: Virtex 4, LVDS I/O: Sanity check please

We'll have >50 devices on a board, in a square array, depending on packing
density and 5 to 10 boards. I'm trying to keep the density high.



The buses theoretically could use a single clock and a single framing signal
for 150 lines, but I know that's not practical. I'm assuming 15 8-bit buses
with individual clocks and framing on each of the four sides of the chip.
Only two opposite sides will be active at any time. So, 10 lines per bus
for a total of 150 pins total and the same on the opposite side of the chip.
That's 300 lines going at once for over 50 chips on each board. I'm
thinking of burying at least some of the traces internally to minimize EMI.
If I have to use resistors, I will.



I just wanted to make sure that on the surface, assuming good design, there
was nothing patently ridiculous about such a system.


Thanks,

Marco
________________________
Marc Reinig
UCO/Lick Observatory
Laboratory for Adaptive Optics

"PeteS" <PeterSmith1954@xxxxxxxxxxxxxx> wrote in message
news:1153247690.204567.14300@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
John Adair wrote:
Standards like SSTL are good for this due to the low signal swing. The
biggest decision is if to use DCI which burns more power in the V4 or to
use
external resistors which take board area and make routing more difficult.

The other decision is weither you use source synchronous clocking or a
common clock approach. At 150 Mhz the common clock is slightly marginal
depending on how long tracks are, speed grade, etc. unless you use some
DCM
based techniques. You can generate a clock that is offset from the common
clock a little by using a DCM and use that as clock for register input to
gain more time. Alternatively you can use a DCM to null out the clock to
output time and get more margin from that.

John Adair
Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex-4 Development
Board.
http://www.enterpoint.co.uk


"Marc Reinig" <Marco@xxxxxxxxxxxxxxxxx> wrote in message
news:44bc1fed@xxxxxxxxxxx
I have a project where I will have a large array of V4 FPGAs. Each chip
is
intended to connect to its four orthogonal neighbors with no intervening
logic. I would like the number of bus connections between chips in any
direction in the array to be 150 (600 total I/O per chip). The
connections
will be bi-directional. The distance between chips will be the minimum
I
can have with sockets, heat sinks (with individual fans), good layout
and
noise control. Some of the lines, what ever is necessary, will be used
for
clock and framing for the bus data signals. I would like to use DDR.
During bus transfers, all the lines on opposite sides of the chip will
be
operating and the other two sides will be quiescent. I'm hoping for a
bus
clock of 150 MHz.


Comments? ;=)

Marco
________________________
Marc Reinig
UCO/Lick Observatory
Laboratory for Adaptive Optics



If Marc uses SSTL, and uses resistive terminators, I would agree it
takes board space, but I disagree it would make routing significantly
more difficult, except for the sheer number of devices. In a point to
point situation only a series terminator is really required for speeds
up to at least 200MHz / 400Mb/s (I've done it).

Assuming these busses would be bidirectional, external series resistors
would [arguably, at least] actually be better in reducing EMI and
reflections than just DCI (less power too) assuming the devices are
close together (of the order of perhaps 4 inches or less). Much really
depends on the distance. I've used BGA style resistor packs that cram
more resistors into the device than can be done in multipack type SMT
devices. Apart from that, the tiny quad pack devices are particularly
sensitive to even slightly imperfect chip shooters and have a nasty
tendency to crack the resistor, particularly at the ends of the device.

CTS corp makes a particularly nice range of devices
(http://www.ctscorp.com/components/clearone.asp) [I have no affiliation
with them except for having used the parts in the past].

Cheers

PeteS



.

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