Re: Programmable pulse generator

jimwalsh142@xxxxxxxxxxx wrote:
Hi All,

I'm trying to develop a programmable pulse generator, essentially a
single pulse of variable width repeated at a given rate. I posted a
similar question a few weeks ago on sci.elec.design and someone
suggested that this would make a nice CPLD project. As I'm keen to
learn about programmable logic devices I decided to buy a development
kit (Altera 7000 series) and try implementing the pulse generator.

My ideal specification would be pulse widths from 10ns to 10us
incremented in 10ns steps at repetition rates between 1 to 10 kHz. The
evaluation board has a 25MHz clock so I'm limited to 40ns increments
but that's ok for now.

I've been playing around with various counters etc but am struggling
to create anything useful, would be great if someone more experienced
could give me a few hints!?

Where are you struggling ?

For a single pulse, you need a saturating, Reloadable counter - one that loads, counts, then stops when it hits some limit - Commonly 0000.
10us from 40ns is appx 8 bit counter. ( 10-12 bits if you load with BCD thumbwheels)

For linear frequecy rep-rate, that's not quite as simple as normal /N is a 1/X curve.
Choices are a small ROM ( OK for a few Freqs), or a Rate Multiplier or DDS frequency scheme.
With a Rate Multiplier, run it from max Clk, and post-scale to the < 10KHz re-trigger frequency you want, to reduce jitter.

Do you mean 1KHz to 10Khz, or 1Hz to 10Khz ? - former is one decade of Prog Fo, doable in 4 bits of RateMult, latter is 4 decades, so needs
appx 14 bits binary, or 20 bits if you load with BCD thumbwheels.
10Khz to 25Mhz of postscale is ~11 bits binary.

Another pulse-generator approach, is to define the ON and OFF times, then you have just one timing chain, which is a reloadable counter, from two alternating set-values.

That's simple logic, but more set-point wires, or you could choose to compile-in the settings, and use the ISP cable to set. [ Smaller CPLD and less wires ]

-jg


.

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