Re: Programmable pulse generator

<jimwalsh142@xxxxxxxxxxx> wrote in message
news:1154471886.472858.324360@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Hi All,

I'm trying to develop a programmable pulse generator, essentially a
single pulse of variable width repeated at a given rate. I posted a
similar question a few weeks ago on sci.elec.design and someone
suggested that this would make a nice CPLD project. As I'm keen to
learn about programmable logic devices I decided to buy a development
kit (Altera 7000 series) and try implementing the pulse generator.

My ideal specification would be pulse widths from 10ns to 10us
incremented in 10ns steps at repetition rates between 1 to 10 kHz. The
evaluation board has a 25MHz clock so I'm limited to 40ns increments
but that's ok for now.

I've been playing around with various counters etc but am struggling
to create anything useful, would be great if someone more experienced
could give me a few hints!?

Thanks,

Jim W

If you want to do it yourself, are you doing schematic, Verilog, or VHDL?
For the guts you just want a counter that runs from one to your period-1
(after which it rolls back to 0) and a comparator for the number of cycles
for your output pulse high. The registered comparator output give you a
nice, clean, programmed pulse.

If you had a 100 MHz source, 10 us would require a count to at least 999 or
10 bits. This 10-bit counter also needs two 10-bit values, one for the
period and one for the high width. The 10-bit comparator should implement
nicely in the CPLD. The two 10-bit values need to be written into the CPLD
in some form. If your load signal is asynchronous, be aware that changing
the setting may present an unexpected glitch or runt pulse. Let us know if
you need to avoid a single bad pulse when changing settings.

Also, do you have more than 32 Macrocells to work with and want more bells
and whistles?


.

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