Post Place and Route simulation for Microblaze....

Hi guys,
I posted my problem a few days ago but I think I didn't make my points
clear so I've decided to post it again.
I have a very simple Microblaze based system which just has the
processor and LMB BRAMs for instruction and data. I'm running my code
on this system and I basically want to measure the power consumption of
the system. I've generated a .vcd file by behavioral simulation of my
design and estimated the power with that. But it seems that it is far
unrealistic. As well by behavioral simulation I could verify my system
behavior. I was monitoring my ilmb_lmb_abus which was the address bus
of the instruction port of the microblaze and on the other hand I had
the assembly code of my software so I could see what's going on in the
system. However now to get a better estimation of power consumption of
my system I want to do Post Place and Route simulation and generate the
..vcd by doing so. I've made sure that there is data in BRAMs in
system_stub_timesim.vhd file generated by ISE. But when modelsim
simulates my design I observe irregular fetches on my address bus. Even
the contents of the addresses which should be the opcodes of the
instructions doesn't match with the assembly file that I have. I'm also
monitoring Program Counter value but that one too has irregular
patterns in addresses though different from address bus. I'm trying to
verify my simulation to make sure that the .vcd file that is generated
is what it should be however I'm stuck here because I don't know what
the problem is.
I am wondering if any of you have any idea what is going on and what
can I do about it,

I really appreciate your response and thanks alot beforehand,

Amir

PS. By the way I'm using ISE 8.1.03i and EDK 8.1.01i and Modelsim SE 6.0

.

Relevant Pages

  • Re: Modelsim VCD files
    ... But the VCD file breaks the bus into individual signals. ... The VHDL is defined as: ... VCD comes from Verilog and I am not sure the language support ranges. ...
    (comp.lang.vhdl)
  • Re: How to gnerate VCD file with hex outputs.
    ... You could write a program to parse the VCD file and translate ... individual bit changes into changes on a bus. ... As for an option in the GUI in modelsim to generate vcd files, ... using will do this for you though - I think there's an option in Xilinx ...
    (comp.arch.fpga)
  • XPower: Cant change activity rates
    ... I have created a .vcd file using modelsim and am trying to estimate the power consumption for my design. ... The problem is when I load this vcd file in the XPower it gives warnings as shown below. ...
    (comp.arch.fpga)
  • grouping bits to form bus in VCD file
    ... I try comparing the VCD files generated by Modelsim to a reference VCD file. ... So is there a way to group single bits in VCD to a single Bus? ...
    (comp.arch.fpga)
  • Grouping nets in VCD file
    ... When I use the $dumpvars instruction to capture a bus and run the simulation in Modelsim, the bus is broken into individual nets in the VCD file. ...
    (comp.lang.verilog)