Re: Micorblaze post place and route simulation...

hmm,
Thanks for the information but after all do you have any idea why this
happens? Am I on the right way of verification at all? Because I want
to measure the power but I have to make sure that the generated vcd
file has correct information.

mk wrote:
On 13 Jul 2006 03:18:17 -0700, antti.tyrvainen@xxxxxxxxxx wrote:


mk kirjoitti:


By the way, why do you perform post P&R simulation for power analysis?
Isn't functional simulation activity output enough?
Do you know if post P&R simulation really gives a benefit over
functional simulation for power analysis?

Antti

With current FPGAs where routing delay can be more than half of the
total delay, p&r results can be quite important in power. How long a
route is and how many buffers it goes through certainly impacts the
power consumption.

Yes, but does the power tool really need post P&R simulation .vcd for
that?
Isn't P&R netlist enough?

Can't you use functional .vcd together with post P&R netlist?

Antti

I am not sure what you mean by functional simulation here. If you mean
rtl simulation, the answer is no; the nets and the gates (including
replicated flops etc) have to match to get an accurate number. If you
mean p&r netlist without the associated SDF back-annotation, that
would be ok, you don't need timing annotated simulations. VCD gets the
changes in the design so you have to simulate what ever is happening
in the chip, not necessarily with timing.

.

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