Re: Micorblaze post place and route simulation...

On 13 Jul 2006 01:49:22 -0700, antti.tyrvainen@xxxxxxxxxx wrote:

amirhossein.gholamipour@xxxxxxxxx kirjoitti:

Hi guys,
I'm trying to do post place and route simulation and generate vcd file
to estimate the power with XPower. I tried behavioral simulation and
the system was working fine.

Thanks alot beforehand,

Amir

By the way, why do you perform post P&R simulation for power analysis?
Isn't functional simulation activity output enough?
Do you know if post P&R simulation really gives a benefit over
functional simulation for
power analysis?

Antti

With current FPGAs where routing delay can be more than half of the
total delay, p&r results can be quite important in power. How long a
route is and how many buffers it goes through certainly impacts the
power consumption.
.

Relevant Pages

  • Re: More Failed Autos Coming Soon.....
    ... simulation, I'd asked them a couple years running if they could demonstrate ... Thanks Bell. ... and all the autos were to touchdown, no power recoverys. ... Also did about every kind of failure I can imagine and others I never ...
    (rec.aviation.rotorcraft)
  • Re: Verilog and PCB layout
    ... pinouts between the board netlist and the HDL source. ... e.g. power supply connections. ... connection fault in simulation. ... then I'm in the "design & review" camp. ...
    (comp.lang.verilog)
  • checkpoint-restart (was Re: suspending programs)
    ... and restart them later on. ... The jobs may be running on a ... and to facilitate simulation or modeling. ... restart with power back on. ...
    (Debian-User)
  • Re: Micorblaze post place and route simulation...
    ... to measure the power but I have to make sure that the generated vcd ... why do you perform post P&R simulation for power analysis? ... Isn't functional simulation activity output enough? ...
    (comp.arch.fpga)
  • Re: Micorblaze post place and route simulation...
    ... why do you perform post P&R simulation for power analysis? ... Isn't functional simulation activity output enough? ...
    (comp.arch.fpga)