Re: Weird JTAG lockup issue, where is the BUG?

I didn't think that was the problem, but I thought I would throw it out
there. Bizarre problem indeed. Please post when you find the answer.

"Antti" <Antti.Lukats@xxxxxxxxxx> wrote in message
news:1152471480.276262.151590@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Rob schrieb:

I'm not that familiar with Xilinx's FPGA's; but I did have an issue with
an
Altera FPGA that turned out to be power supply related. The problem was
that the power-up configuration was unstable, sometimes it would work and
other times it wouldn't. But, if I powered up, then initiated a
configuration (from an on board push-button), it always worked. This led
me
to look at the power rails. In my case, I had a power supply that was
generating a non-monotonic rise on VCCint. Once I fixed the rise so that
it
was smooth the problem went away.

Can you initiate, or re-initiate, the configuration cycle after you are
powerd up and the voltage rails are stable? If so, try it, and see what
happens. It may give you another clue.

Take care,
Rob

Hi Rob,

1) I can configure and reconfigure the board with many many different
designs and never see an issue at all.

2) when using one specific design/bitstream then I can configure and
reconfigure any number of times when Xilinx impact is set to perform
configure and verify. Impact even reports programming and verify
success !!

3) using the same bitstream and impact with configure, but no verify
then first configuration attempts says configure error (CRC error) and
after that the JTAG chain is reported as broken before the FPGA. The
power supplies are still proper Voltage and stable and the FPGA does
not get hot. But it needs to be power cycled for the JTAG TAP to come
live again.

I understand that power supply is the most likely issue but why doesnt
the issue never happen when jtag operation is set to
configure_and_verify? and locks up the jtag tap 100% when attempting to
configure without verify?

I bet this remains "Xilinx mystery" forever.

Antti



.

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