Re: Xilinx BUFGMUX Setup Time requirement clarification needed

Asynchronously switching between two unrelated clock frequencies is an
interesting task. A simple solution is described as the last item in my
"Six Easy Pieces" TechXcusives of many years ago. That circuit,
however, has one problem: it cannot switch away from a dead clock.
No problem when both clocks run continuously, but still a limit to the
generality of the solution.
Avoiding that little problem is extremely difficult, and several
generations of BUFGMUX circuits have unfortunately destroyed the basic
concept of asynchronous control in the laudable attempt to cover the
Achilles heel. (Siegfrieds Lindenblatt for the Germans, same concept,
As we know, both heroes sadly died because of their tiny problem area).
If your clocks are always running, welcome to "Six Easy Pieces".
Peter Alfke, Xilinx
===========
Uwe Bonnes wrote:
Hello,

e.g. the XC3SE Data*** ds312 tells on page 59 in the Clock
Buffers/Multiplexers section:

"As specified in DC and Switching Characteristics (Module 3), the select
input has a setup time requirement."

This is probaly Tgsi on page 139.

What can happen if the setup time is not met ("End of the world as we knew
it?:-)) ? Does the select signal need to be aligned to both input clock
edges? If it needs to be aligned to both clocks, how does one achieve
that. An if there are that harsh requirements on the select signal, what's
the whole point in the BUFGMUX?

Or does the select signal only needs to be aligned with the active
edge. Simple latching the enable signal with the BUFGMUX output clock and
feeding the latch output to the select of BUFGMUX would do the job (beside
the case where the active clock is slow, where the time to the next clock
would be needed before the clocks would switch.

Some clarification would be fine.

--
Uwe Bonnes bon@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
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