Re: Stopping the clock for power management
- From: mikeandmax@xxxxxxx
- Date: 29 Jun 2006 16:22:18 -0700
Ndf wrote:
Hello,>
For a low power application I would like to stop the clock feed into a FPGA
when enter "sleep mode". This is a common practice or can be dangerous? And
if is dangerous why? Maybe a silly question but I want to be sure about
that! I use Lattice XP parts.
Thanks,
Dan.Hi Dan -
this is actually a 2-parter -
LatticeXP devices have DCS blocks(Dynamic Clock Selection) as part
of the global clock networks, and can be used to deactivate selected
clocks, reducing current for that clock domain.
LatticeXP, and MachXO, both also offer 'Sleep Mode', in that these
devices have built-in Flash memory, for boot-up. The SleepMode pin
deactivates the core power supply, and maintains voltage in the I/O,
which allows for very low power ( less than 100ua) standby current.
When exiting 'sleep mode' the core supply is re-activated, and the
device then auto-boots from flash on chip.
The marketing term is "INSTANT ON" but us FAEs prefer "less than 1
millisecond". :)
So, yes, you can disable clocks to save some power, while the device
remains active, or you can enter 'sleep mode' and save most of the
power. Sleep Mode is available on the 'C' version of each device in
the family. The 'C' version has an onboard regulator, so you can run
the device with a single 3.3v supply. The core operates at 1.2v,
(derived from the on chip regulator in the 'C' devices), we require
3.3v for VccAUX(used for thresholding and some housekeeping circuitry),
and the appropriate VccIO voltages.
thanks for aking -
Michael Thomas
Lattice SFAE - NY/NJ
.
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