Re: How to evaluate the space efficiency of a historic design.

mk wrote:
Let me do a rough calculation here:
9000 transistors assuming 6502 had no memory can be used to generate
2250 2 input NAND gates. S3200 has 4320 logic cells (1 flop + 1 lookup
table); assuming a 4 input look up table is around 3 nand2 and a flop
is around 5 nand2, I'd say it has 34560 equivalent nand2s so 25% would
be 8640 gates and that would be around 4x too big; again very roughly
and I am sure lots of people would disagree but I think it's a
reasonable starting point.

Well, when your basic building block is the transistor, you can
implement a lot more logic pr transistor than when it's just a NAND
gate. Add to that the fact that setting 1 LUT = 3 NAND2 is really
unfair to the FPGA as there will be lots of logic that don't come near
that utilization of the LUT. Thus, I'd say that it's probably only
about 2x too big.

The real problem is the premise of comparing LUTs to transistors and
you can in fact do much better than that. After mapping, you are told
much more detail of how resources were used, say how many were FF,
LUT2, LUT3, etc. Make an estimate of how many transistors you would
need for each (say a LUT2 is somewhere between a NAND and an XOR).

Don't forget to keep the original 6502's interfaces the same if you
want an accurate model.

Tommy

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